Electronic Design
Data Management For EDA Apps Sees Gains In 2011

Data Management For EDA Apps Sees Gains In 2011

As EDA edges closer and closer to becoming a commodity, even if the products that EDA tools are used to create are not, the best EDA products and technologies often are refinements of existing technologies. That doesn’t mean the gains from these refinements are incremental or insignificant. To the contrary, this year’s Best EDA winners both have gone a long way toward smoothing out major elements of the design process for system-on-a-chip (SoC) and printed-circuit board (PCB) design teams.

Designers And Foundries

For example, consider the large language gap that yawns between chip designers and their foundries. Designers speak of their creations in terms of gain, delays, power, timing, hierarchy, blocks, and errors. At the foundry, however, the discussion is of mask layers and defects. For some time, Mentor Graphics’ Calibre suite has linked these disparate worlds, putting what designers see in terms that the foundry can understand.

Meanwhile, physical verification is becoming an extremely complex undertaking. There are about twice as many rules at the 28-nm node as there were at 90 nm (Fig. 1). Under these conditions, getting a design to a state in which the fab will ensure manufacturability is a stressful process. It is highly iterative and fraught with long runtimes. Sometimes manual design-rule checking (DRC) fixes introduce new errors. Thus, designers often stop trying to optimize their layout as soon as they see a “clean” DRC result. The alternatives are to take even longer to get a layout done or to hire more layout engineers.

Mentor’s response has been to bring Calibre forward into the design process. This migration really began with last year’s launch of Calibre InRoute, which put the Calibre engine inside the cockpit of the Olympus-SoC router. The next step came earlier this year with the launch of Calibre RealTime, which comprises an integration of Calibre signoff design-rule checking with the SpringSoft Laker custom design environment.

The pairing of Calibre RealTime and Laker is implemented with the OpenAccess runtime model. Together, the tools give layout designers signoff-quality DRC as they make changes, using standard Calibre rule decks. When designers edit a polygon, path, or device placement in Laker, Calibre automatically runs DRC on that change and delivers results immediately without ever leaving the familiar Laker editing cockpit.

It all happens rather quickly, too. In a test of a large 28-nm block, about 3000 checks on 6649 shapes returned results in 0.2 seconds. Add that up across a full standard-cell library and you’re saving lots of time over older methodologies, where a similar DRC check might take from 10 to 20 seconds. Designers gain a lot more time to optimize their work.

When performing routing either manually or automatically in Laker, Calibre detects changes as they are made and finds signoff errors referenced against the golden rule deck that may not be in the internal tech file. As designers instantiate and modify PCells or MCells, Calibre is again automatically invoked to ensure that the cells are placed without creating violations in the layer being worked on or in adjacent layers.

From IC to PCB

Of course, SoCs don’t exist in isolation but must be integrated into an overall system design, which leads us to PCBs. PCB design teams must keep up with a ton of information. Not only are these teams frequently geographically dispersed, they also comprise individuals with expertise in different domains.

Then there is the data itself, both that which concerns the circuit and board layout and that which concerns the components and intellectual property (IP). The latter is a highly dynamic set of data coming from multiple sources, including distributors and manufacturers.

The Altium Designer suite has gone through a number of revisions over its lifespan, many of which have sought to address this growing issue. With this year’s release of Altium Designer 10, the company has arrived at a milestone in its efforts to tame the design-data beast.

Many things can happen in the context of design data that can derail the design team: price/availability changes related to components, change-management miscues, ECO management, IP management, and release management, to name just a few. Altium Designer 10 handles this amalgam of data through a unified data model, which pairs with a single executable.

According to Bob Potock, Altium’s director of marketing in the Americas, this approach trumps that of competitors whose flows are less organic in nature. “The unified data model and data-management layers were developed concurrently,” says Potock. “This provides a great foundation for the design tools at the next layer.”

That design-data management layer, which Altium has dubbed Altium Vaults, enables designers to store and manage design data and revisions. It also lets them manage component lifecycles and track usage of components across designs. Further, it contains links to the supply chain and manufacturing. “All of this data is very dynamic. In the supply-chain databases, hundreds of parts are added and/or updated daily,” says Potock.

The implications of the data-management problem become clearer when considered from the standpoint of product development. Component data comes from manufacturers such as Xilinx and Texas Instruments. On top of that is a layer of distributors such as Arrow, Digi-Key, and Mouser. This information enters through a business system and then propagates into the design process.

Feeding from this profusion of data are various domain-specific design processes, and the data must move within each domain and across them. Imagine a circumstance in which a high-pin-count FPGA in your design needs to be pin-swapped at the PCB level. This design change must propagate into the FPGA design process. Typically, this non-trivial exercise involves two separate tool chains. Altium Designer 10 makes this process a pushbutton affair.

Altium Designer 10 presents engineers with a hierarchical project view that enables collaboration (Fig. 2). At the top level are all PCB-related design files, and inside the PCB project is the onboard FPGA project. Inside the FPGA, if you were using an embedded processor, would be the software development project for that processor. The project view also provides for version control, which encourages a fluid, iterative design process.

The Enterprise Vault has three data zones. These zones connect to the outside world of distributors, business systems, and manufacturing partners. With all of the component data in the Vault, it becomes a simple matter to trade off criteria to aid in making design decisions.

Finally, when the design achieves maturity, data integrity checks ensure that everything is correct. Altium Designer 10 verifies that all parts on the bill of materials are approved and that the schematic and PCB layout are in sync. It also runs design-rule checking.

Another key addition to Altium Designer 10 is a feature called AltiumLive, which is an implementation of cloud-based services for software downloads and maintenance. Using AltiumLive, users can customize their initial installation of Altium Designer 10 and then use it subsequently to change their installation as needs evolve. With AltiumLive, there are no more service packs when updates occur but rather cloud-based updates.

A second element of AltiumLive will be availability of design content and IP. The first design content comes from Altium’s technical centers in Shanghai and in Hobart, Tasmania, Australia. In the future, the ecosystem will be opened to user contributions.

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