Electronic Design

Design Platform Orbits At A Higher Plane Thanks To Upgrades

Across-the-board boosts in runtime, capacity, and quality of results (QoR) are the aim of a major upgrade to Synopsys' Galaxy design platform. Galaxy 2004's improvements reach every stage of the design flow, like RTL synthesis, design planning, power management, signal integrity, and testability. All of its tools now use identical constraints, libraries, and delay calculations.

Performance gains come throughout the entire flow. Design Compiler sports twice-as-fast runtimes with 40% more capacity and 10% better QoR on area than the 2003 release. A simplified synthesis flow lets designers run a top-down compile for large blocks on a 32-bit workstation for even greater runtime improvements. The tool supports SystemVerilog as well.

The JupiterXT design planner now offers twice the capacity of last year's version as well as a threefold speed improvement in the time required to create a detailed floorplan. Physical Compiler offers runtime that's twice as fast, a 100% capacity gain, and 15% better QoR on timing. Its new distributed physical synthesis capability distributes large, flat designs over multiple CPUs for faster turnaround. The Astro place-and-route tool offers 50% more capacity, TCL command-line support, and simpler library preparation.

PrimeTime, Synopsys' static-timing analysis tool, brings a threefold improvement in both runtime and capacity. It also now supports instance- and net-specific timing derating for improved support of on-chip variation.

Synopsys
www.synopsys.com

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