Electronic Design

Design Workable Thermal Management Solutions Into Your Next Product

The challenge of removing heat from ICs has increased significantly. It’s no longer just at the chip level, though. It has grown to include hotspot formation on boards. The emergence of nano-electronics, which employ 90-nm process technology and will reach 32 nm by the end of the decade, has led to localized areas of high heat flux that dominate the performance of electronics at the chip level.

The same problem exists at the board level. This is where monolithic microwave integrated circuits (MMICs), MOSFETs, and other power devices are moving ever closer to components such as displays that are extremely sensitive to high heat fluxes.

All too often we consider and design devices from a performance point of view first and only later consider the thermal management system we require to support their reliable performance. The necessary thermal management system then must integrate as an add-on unit that must fit within what little space is available in the existing system.

The development of localized die- or board-level thermal management solutions entails the integration of thermoelectric material into a flip-chip solder bump. Designers can then place these thermal bumps inside electronic packages. Development of the thermal bump serves the purpose of integrating active thermal management functionality at the chip level in the same manner that transistors, resistors, and capacitors integrate into conventional circuit designs today.

Several methods are available for mitigating the effects of die- and board-level hotspots through localized cooling of the on-chip heat source or by producing temperature inversions to manage the heat flow. It’s possible to integrate this thermal management approach onto a chip or package level layout tool to provide for real die thermal design solutions. Also, several innovations are driving new approaches in electronics cooling.

The thermal copper pillar bump, or thermal bump, consists of a thin-film, thermally active material embedded into flip-chip interconnects, in particular copper pillar solder bumps (Fig. 1). Unlike conventional solder bumps that provide an electrical path and a mechanical connection to the package, thermal bumps act as solid-state heat pumps pulling heat from one side of the device and transferring it to the other as current passes through the thermoelectric material.

Thermal bumps offer many advantages in terms of size, efficiency, and powerpumping capability. Today’s common thermal bumps are extremely small, in the realm of 110 µm in diameter by 65 µm high and are scalable to accommodate different sizes for a variety of applications. The bump adds as little as 100 µm of thickness to a heat spreader, enabling unobtrusive integration close to the heat source.

It isn’t uncommon for thermal bumps to achieve temperature differentials in excess of 60°C between the top and bottom headers. They additionally exhibit powerpumping capabilities exceeding 150 W/ cm2. Naturally, this makes thermal bumps viable contenders for applications involving high heat-fluxes.

Today, we can introduce thermal bumps into systems at either the chip level or the board level using discrete modules. We can design thermal bumps in for heat removal from the back or front of the die and even laterally (Fig. 2, again). There are several integration possibilities.

Designers can enhance back-side cooling by introducing thermal bumps into the heatsink to form an active heatsink or into a heat spreader. In this case, we employ discrete devices to mitigate hotspots emanating from the front of the die. In fact, while the following example demonstrates the feasibility of hotspot cooling using integral thermoelectric cooling, it also reveals the limitations of cooling the hotspot from the back of the die.

The hotspot sits on the active side of the die while the cooling device attaches to the copper heat spreader. The heat spreader is flipped onto the back of the die so the cooler is located near the back of the die, behind the first level thermal interface material, or TIM1.

In the lateral cooling paradigm, current flows from left to right, but the heat flows from the center of the module outward (Fig. 3). For a 3D chip stack, this lateral heat removal concept is combinable with an interposer through which the heat can shuttle away from the device.

In this scenario, the thermoelectric material is underneath the substrate and pulls heat from the center segment to the side. In turn, the center of the platform will cool, the sides will become hotter, and the heat dissipates laterally into the walls.

The last approach is active-side cooling. Figure 4 depicts the active side of a microprocessor. The smaller structures in the closeup represent conventional copper pillar bumps next to the larger thermal bump. There could be as few as 10 to 20 or as many as 600 to 1200 thermal bumps strategically placed on the chip only in the vicinity of the hotspots.

For this application, it isn’t necessary to use a large amount of thermoelectric material. In fact, as little as 1 by 1 mm per hotspot would be necessary to achieve the desired cooling effect. Notably, placement of this material so close to the heat source would lead to a higher thermoelectric cooling (TEC) efficiency.

We can address hotspots on printedcircuit boards (PCBs) using discrete modules, strategically placing them near the source of heat. Metal traces, which can be several microns thick, can be stacked or interdigitated to provide highly conductive pathways for collecting heat from the underlying circuit and funneling that heat to the thermal bump. Additionally, adding thermal vias, i.e., copper filled vias, will be necessary to provide pathways for the dissipating heat.

Managing the heat flow in systems is also a problem for many manufacturers of mobile devices. Unlike electromagnetic energy, which designers can isolate and/or confine, heat is mechanical in nature and hence can flow in any direction. This may include flowing toward sensitive components such as LCDs and other delicate parts. One solution is to employ thermoelectrics to create a thermal barrier against the flow of this energy.

A thermal barrier creates a small temperature inversion that channels thermal energy away from the barrier and in a more desirable direction. Construction of a thermal barrier may consist of several discrete thermoelectric devices, however loosely spaced and powered only at a very low level (Fig. 5).

The overall design, the number of modules, their spacing, and the heat spreader materials and dimensions determine the characteristics of the thermal barrier. In most cases, a 3°C to 5°C temperature inversion is all that is necessary to cause the heat to flow away from a surface, in essence creating a mirror or thermal reflector. The thermal barrier can activate when the temperature of the board reaches a critical point, creating an on-demand thermal management solution.

The use of thermal bumps and discrete devices to provide a thermal management solution does not obviate the need for system- level cooling or for a reasonable means of rejecting heat out of the system. Rather, it offers system design engineers a new set of tools with which to shape and enhance the performance of their system. Ultimately, the focus should be on cooling what you need to cool and nothing else and then managing the removal of this heat in a controlled fashion.

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