Designing Chips For JTAG Testing

Dominic Plunkett believes chip designers should do more to ensure full compliance to the IEE1149.1 JTAG boundary-scan standard.

Boundary-scan testing offers a solution to the challenges presented by high component density, increasing use of area array packages, and the prevalence of complex, multilayer PCBs, which make test probe access and bed-of-nails testing impossible for many new board designs.

Modern JTAG test gear has powerful capabilities that add value to product development, production, and field maintenance. Graphical user interfaces along with powerful test generation and troubleshooting capabilities make the tools extremely easy to use. But successful adoption of JTAG to solve the underlying test challenges depends on the commitment of semiconductor manufacturers.

They must provide silicon that meets JTAG specifications, as well as provide scripts that accurately describe the device characteristics for the benefit of JTAG test gear. In other words, we need dependable, tested BSDL files.

Some manufacturers are commendably committed to ensuring JTAG compliance. Among these, FPGA manufacturers are arguably the largest users of probe-unfriendly area array packages, with the most pins available for JTAG access as well as the most experience of reconfiguring pins to maximise user I/O. However, designers need more JTAG-compatible components, including ASSPs, memories, MCUs, transceivers, and controllers, to configure comprehensive JTAG chains and thereby maximise test coverage. But JTAG-compatible components need to be just that—chip designers must ensure they are fully appraised of the JTAG specifications, aware of the internal logical requirements and sequences.

The same is true for the supporting BSDL file. Untested, poorly written files can cost end-product designers dearly in terms of wasted troubleshooting time.

Of course, it is not possible for every device to be made JTAG-compliant. There may be good reasons—for example, insufficient available pins to provide four pins for JTAG access. Also, it may not be possible to arrange pin sharing. Good, modern JTAG test equipment is able to test even non-compliant devices, provided they can be accessed by compliant devices in the same net. But even here, chip manufacturers can do more to support higher levels of boundary-scan test coverage.

Many do not make adequate provision to run the device slowlyas required by JTAG, for example. If the device will not behave as intended below the minimum specified frequency for normal operation, a carefully constructed JTAG test script will return meaningless results. By engineering alternative operating modes that are JTAG-friendly, manufacturers of non-JTAG chips will be able to help their customers raise test coverage by including their devices as part of an overall JTAG strategy for the board.

Admittedly, it is not necessary for every component to be JTAG-testable from outside the chain. The entire electronic value chain, from wafer fabs to end-product designers and assemblers, to repair and maintenance engineers, need high-quality test solutions that safeguard high test coverage. But fear of reduced testability is holding back product designers; one manifestation is slower than ideal adoption of new component technologies, such as chip scale packaging.

But because JTAG calls for the involvement of silicon designers, and is extending its role into all stages of the product lifecycle through the enhanced capabilities of the latest JTAG test gear, chip manufacturers and end-product designers can work together to solve the challenges of test and testability.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish