Squeeze more functions onto a silicon chip—so what else is new? Getting that circuitry in ever smaller packages, though, can be a real head-scratcher. Two major hurdles stand in the way of these twin goals that, when met, can lead to a product's mass-market success: keeping costs and weights down, and bringing a product to market rapidly.
As devices become smaller and operate at higher clock frequencies, they edge into the RF arena and dissipate more power. Getting a better handle on controlling heat dissipation and bringing down power-consumption levels become more difficult. Many EDA vendors offer thermal modeling programs to help here.
One factor, the use of lower IC operating voltages, has brought some help. But it doesn't do much for power ICs that by their very nature dissipate lots of current. Even for purely digital IC designs like the latest high-speed microprocessors, heat management is a big concern. Basic elements like decoupling capacitors, which themselves are shrinking, can contribute large inductance effects in the microprocessor's interconnects, degrading performance.
IC and package designers, who for years worked in separate camps, are getting smarter. They're pooling their resources to come up with the ultimate combination that's optimized for package-level integration as well as silicon-level integration. This is exemplified in multichip-package (MCP) and system-in-a-package (SiP) technologies.
Realistically, there's one way to gain more packaging functional densities: Use the vertical dimension, creating 3D packaging. It has veered somewhat from its original concept, though. Today's 3D packaging involves stacking multiple dies and packages within a package. But in true 3D packaging—the concept that IC chip designers talk about—the package holds a single die with all of the electronic functions on the die.
IC and package designers recognize that not everything can be successfully integrated in a single system-on-a-chip (SoC) package. Logic and memory circuits with motor drivers, MEMS devices, and RF circuitry can't be combined in an SoC, at least not yet. Sometimes, optimized solutions of two or three packages connected together are the answer for today's market demands. There's no denying that increasing RF IC integration levels are resulting in ICs with both increasing pin counts and proportionately increasing package sizes (Fig. 1) .
BEYOND THE CHIP
Packaging design challenges rise more sharply when a packaged chip or chips must be laid out on a pc board. Parasitic package inductance can easily create ground bounce and VCC signal bounce on the board.
While some modeling and electrical effects information is available from IC vendors, there's a dearth of info when it comes to board layout. That's unfortunate since board designers far outnumber chip designers. Reasons behind the lack of pc-board packaging models and data sheets stem from the lack of a standard definition of terms and taxonomy for this area.
Intel Corp. has studied the board packaging problem. Its Type II board technology uses buried vias and micro vias as well as smaller feature sizes than the average pc board, which employs plated-through holes. Intel notes that as board-routing capabilities increase, the large size and pitch of the plated-through hole can constrain the shrinking of a ball's pitch for common ball-gridarray (BGA) packages. Whereas a standard BGA ball pitch of about 0.8 mm is possible using pc boards with plated-through holes, the Type II board trims this to 0.6 mm.
POWER DEVICES POSE CHALLENGES
Some notable advances have occurred in monolithic power-controller ICs, often called "smart power" ICs. They now combine analog, digital, and power semiconductor circuits on the same chip, thanks to improvements in IC processing technology.
But these ICs are limited in power-level capability, and they don't handle the power levels of discrete power ICs. Just one of many examples is the LM5026, a 100-V pulse-width-modulated (PWM) controller from National Semiconductor. The firm's voltage-scaled ABCD (analog biCMOSDMOS) process makes this possible.
Some experts are calling for a new approach to packaging discrete power ICs. They see a need for new substrate materials like silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN), as well as radically different circuit topologies like single-cycle control, matrix converters, and bidirectional switches.
STATS ChipPAC Ltd. offers one approach to dealing with heat and package size. The company has shown that a 3D power package using a hybrid lead-frame integration concept can be very useful. The two-package stack with standard die layout (same size die) saves 50% of the real estate on system boards (Fig. 2).
THE TRUE 3D APPROACH
Some monolithic purists doggedly pursue a complete 3D silicon IC wafer within a small package, using the same process. But only time will tell if they can include many power functions in one package, as well as other functions that aren't possible yet. Certain indications bode well for this approach, including the ability to put analog signal-conditioning, sensor, and imaging circuitry on the same chip housing memory and logic.
At last year's International Electron Devices Meeting (IEDM), a group of researchers at Japan's Tohoku University reported on a planar large-scale-integration (LSI) process with which they can build a "super" 3D chip consisting of stacked wafers (Fig. 3). They've since formed a company, called ZyCube, that intends to offer samples of such an LSI chip this month.
Known as Super Smart Stack technology, the concept already was proven for chips containing static RAM. The key process issues in developing this chip were wafer alignment, buried interconnections, the use of micro bumps, wafer thinning, and the use of an adhesive layer.
ZyCube foresees many potential applications for the chip, including the development of a communication processor system, a brain information-processing chip, a 3D artificial retina, and robotic vision. Beyond the sampling stage this month, the company feels confident that the next development to succeed will be an artificial retina, though no time frame is available yet.