Electronic Design

Digital

Speedy Serializer-Deserializer Moves Data At 3.125 Gbits/s
The Quad SerDes (serializer-deserializer) core can transfer data at 3.125 Gbits/s. Differential signalling is employed to ensure data quality at the receiving end. It can be used in high-speed networks or to create virtual backplanes that reduce the wiring clutter when moving packets from board to board. The device also offers four sets of differential pairs that, combined, supply a total data throughput of 12.8 Gbits/s. This high throughput lets the cell support the 10-Gbit/s full-duplex rate, which is already in widespread use in network line cards that provide interfaces to OC-48, OC-192, and other standards. A second-generation SerDes chip will handle 5 Gbits/s per differential pair. Implemented using a low-cost standard CMOS process, the cell can be fabricated by any foundry capable of handling the 0.18-µm feature sizes.

Available for licensing to foundries, ASIC suppliers, and even FPGA manufacturers, the Quad SerDes cell is immediately available. License fees are determined by volume and degree of support required.

Rambus Inc., 2465 Latham St., Mountain View, CA 94040; (650) 944-8000; www.rambus.com.



DDR SDRAMs Deliver 32-Bit Data At Clock Rates Of 150 Or 166 MHz
Available at clock speeds of 150 (the MT46V2M32LG-65) or 166 MHz (the MT46V2M32LG-6), a 2-Mword by 32-bit double-data-rate (DDR) SDRAM gives designers a high-bandwidth and cost-effective solution for graphics, networking, and telecom applications. The company also offers single-data-rate (SDR) 2-Mword by 32-bit devices and 1-Mword by 16-bit SDRAMs that clock at 143 and 166 MHz.

Production volumes of the 150- and 166-MHz models will be available this quarter, and a 4-Mword by 16-bit version of the DDR SDRAM will be available next quarter. The company expects to offer the chips in 183- and 200-MHz speeds sometime next quarter as well.

Housed in a standard 100-pin TQFP, samples of the 150- and 166-MHz versions are immediately available. Prices for these memories are comparable to those of equivalent-capacity SDR SDRAMs.

Micron Technology Inc., 8000 S. Federal Way, P.O. Box 6, Boise, ID 83706; (208) 368-4400; www.micron.com/mti/msp/html/ddrsdramprod.html.



Low-Voltage Flash Memory Trims Sequential Access To 20 ns/Word
A 1-Mbit low-voltage flash memory, the M59BW102, can sequentially access data at just 20 ns/word when used in its burst mode. The chip also has a 25-ns cycle time and a 55-ns random-access time. Designed for operation from a 3-V supply (for both reads and writes), the flash memory is organized as a 64-kword by 16-bit array. It's designed for applications such as program storage in magnetic and optical disk drives.

Fabricated with 0.35-µm design rules, the entire flash memory can be erased with a single signal and then programmed word-by-word in system. Instructions for read/reset, programming, chip erase, and autoselect for reading the electronic signature are written to a command interface using standard microprocessor write-timing signals. The chip is specified for 100,000 program-erase cycles and 20-year guaranteed data retention. It retains the same TSOP40 package footprint as the company's previous M29F102BB/B flash memories.

Samples of the chip are immediately available. In lots of 10,000 units, it sells for $3 apiece.

STMicroelectronics Inc., Lexington Corporate Center, 10 Maguire Rd., Bldg. 1, 3rd Floor, Lexington, MA 02421; Peter Canova, (949) 347-4711; www.st.com.

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