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Standard Logic And Interface Devices: Still The Glue That Binds

Even as the IC industry continues its march toward total system-on-a-chip (SoC) solutions, there will always be a need for a gate here, an inverter there, a level translator somewhere else, or a stable clock source. Thus, standard logic survives, albeit in a different form than a decade ago.

Gone are the huge catalogs of standard transistor-transistor-level (TTL) building blocks, with most of the logic elements replaced by 68-pin and smaller programmable logic devices. Only a few discrete functions survive, and those are mostly logic-level translators, bus buffers/drivers, and data latches. The one exception is the growing popularity of single-gate logic functions—gates, inverters, flip-flops, and so forth, each housed in packages as small as a spec of dust. These devices can be "sprinkled" wherever necessary in a system and make almost no impact on board area.

Taking aim at portable systems' need for low-power operation, designers at Texas Instruments have developed a family of low-power logic devices called the advanced ultra-low-power (AUP) logic family. The AUP logic circuits deliver a considerable power savings over traditional 3.3-V logic technologies. They consume 91% less static and 83% less dynamic power than the industry-standard 3.3-V logic technologies. This in turn enables the AUP technology to deliver 73% more battery life than 3.3-V logic technologies. The chips' propagation delay is just 2 ns when powered by a 3.3-V supply and 3 ns when running from a 1.8-V supply. Static current is just 900 nA.

Bus buffers/drivers and level translators are critical elements in today's high-speed systems. As buses get wider and faster, the buffers, drivers, and translators must also get faster to minimize the propagation delays introduced into the buses. For example, Texas Instruments just released four new dual-supply level-translation transceivers, the SN74LVC1T45, SN74LVC2T45, SN74AVC8T245, and SN74AVC20T245. Targeting portable consumer, networking, datacom, and computing applications, these devices permit flexible bi-directional level translation between 1.5-, 1.8-, 2.5-, 3.3-, and 5-V levels. They are available in 1-, 2-, 8-, and 20-bit wide versions to suit most bus widths.

As buses get wider, the number of buffers and translators also grows. So to help reduce the clutter of packages on the pc boards, companies such as Fairchild, Integrated Device Technology (IDT), Texas Instruments, and other suppliers of such interface circuits are developing wider versions that pack more than 20 transceivers into one package. Propagation delays in high-speed buses can become the performance-limiting factor. The input-to-output delay of the bus buffers/translators then becomes a key issue. Today's best buffers and transceivers can keep the propagation delays to just 1.5 to 2 ns, which will allow bus data rates of 300 to 500 MHz. The vendors are pushing to reduce the delays still further, but the need may not be as great because many of the parallel buses are transformed into multichannel serial connections.

As the parallel buses get wider and faster, they get harder to implement due to capacitive loading and other factors that limit signal speed. To overcome those limitations, several new differential and single-ended serial interfaces have been developed to improve the signaling and increase the data rates. This is especially critical for the memory buses used on the latest-generation microprocessors. Several companies have recently adopted the extreme data rate (XDR) interface developed by Rambus and now available as a block of intellectual property that memory and system designers can license. For non-memory buses, the main action is in converting the buses from parallel to serial to reduce the pin count, provide differential signaling to improve noise immunity, and offer a scalable bandwidth capability.

Chip-level serial interfaces such as HyperTransport and RapidIO and board-level serial interfaces like PCI Express are all growing in popularity. Additionally, generic interfaces based on high-speed serializer/deserializer (SERDES) circuits are starting to replace wide parallel buses with multichannel serial alternatives. SERDES circuits, in the form of standalone chips and blocks of intellectual property with data rates of 1.25 to 3.125 Gbits/s, are now relatively available from multiple sources. Higher-speed implementations, capable of data rates up to about 6.25 Gbits/s, will be sampled this year. And, designers have their sights on 10-Gbit/s SERDES solutions for use in the 2005 time frame.

In addition to all the logic and bus interface circuits, specialized clock and clock-distribution circuits are playing a key role in simplifying systems. In the past, systems often had multiple clock sources, each with its own crystal. Now, multiple output clock generators and buffers, which use just one crystal to generate all the desired frequencies, are available from companies such as Cypress Semiconductor, ICS, and PMC-Sierra, among others. These chips deliver independent, low-jitter, low-skew clock signals that can satisfy the needs of most manufacturers of PC motherboards, network systems, and many industrial computer boards and systems.

See associated figures 1 and 2

TOP TEN

  • EXPECT HIGHER-PERFORMANCE bus interface circuits, with propagation delays below 2 ns, to be sampled later this year. Such chips will allow designers to implement limited-length buses that run at close to 500 MHz.
  • LOGIC LEVEL TRANSLATORS with the lowest power consumption will be available from Texas Instruments. The circuits will have static current drains of just 900 nA and will translate between logic families that employ 1.5-, 1.8-, 2.5-, 3.3-, or 5-V signal levels.
  • THERE WILL BE CONTINUED MOMENTUM in the use of multichannel serial interfaces to replace wide parallel bus structures. For example, parallel buses such as PCI will be replaced by PCI Express, and large parallel backplanes will also include high-speed gigabit Ethernet channels.
  • SERDES BUILDING BLOCKS, operating at 3.125 Gbits/s, will become mainstream. Several suppliers will offer samples of 6-Gbit/s serializer/deserializer (SERDES) solutions.
  • GROWTH WILL CONTINUE in the single-gate logic market as designers work with ever more space-constrained systems. The tiny single-gate logic devices are an ideal solution because their size allows them to be inserted in the system directly in the signal paths. There's no need to make room for a bulky package.
  • MORE-FLEXIBLE CLOCK and clock distribution chips will be available from Cypress Semiconductor and other suppliers. These chips will supply the multiple clock frequencies needed in systems ranging from PCs to network subsystems.
  • INTELLECTUAL-PROPERTY OFFERINGS of both 3.125-GHz SERDES building blocks and more complex interfaces like PCI Express will become more widely available as designers try to reduce system complexity even as performance demands increase.
  • FOR CHIP-TO-CHIP INTERCONNECTIONS, HyperTransport interfaces and RapidIO ports will become mainstream solutions for many systems. There will be a wide variety of support circuits for HyperTransport systems that will enable a wide range of system architectures to be implemented.
  • DIFFERENTIAL SIGNALING INTERFACES will increase in popularity due to their high noise immunity. New interfaces, such as the extreme-data-rate (XDR) interface developed by Rambus, will allow data to transfer at four times the clock speed—up to 6 Gbits/pin.
  • THERE WILL BE CONTINUED price pressure on interface logic as FPGAs and ASIC design libraries continue to absorb more of the system. The system-on-a-chip solutions now in design will require fewer and fewer support functions as designers integrate more of the system, including mixed-signal functions and memory, eliminating the need for any external control/interface logic.
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