Electronic Design

Digital ICs: Standard Logic

Standard Logic: 40 Years And Going Strong

ASICs and field-programmable/reprogrammable logic circuits have absorbed most of the "commodity," or "standard" logic elements—gates, flip-flops, decoders, registers, etc. But there's still a strong demand for certain classes of commodity, small-scale, and medium-scale logic circuits. Some of the circuits include basic gates and flip-flops, but the most activity surrounds bus latches, bus drivers, clock buffers and clock distribution circuits, low-voltage differential-signaling (LVDS) bus transceivers, and serializer/deserializer (SERDES) chips.

Basic logic functions were typically set up with multiple iterations of a function in a single package, quad NAND gates, hex or octal buffers, dual flip-flops, etc. That organization worked well when the majority of system logic was implemented with such packaged devices. Today, the situation is different. Large ASICs and FPGAs swallow most of the logic. Typically, all that's necessary is just a particular gate here, a buffer there, a flip-flop somewhere else, and so forth. Such a need has built momentum for families of single-gate logic elements from most major logic suppliers—Fairchild, National Semiconductor, On Semiconductor, Philips, Texas Instruments, and others. Known as TinyLogic at Fairchild, PicoGate Logic at Philips, and LittleLogic at TI, these devices let designers sprinkle functions exactly where they're needed.

Packaging technology is key when it comes to single-gate functions. Many of these devices are employed in applications with limited board space, and the package footprint and the height are critical concerns. To meet the requirements of these systems, virtually every logic vendor is developing almost microscopic packages, barely larger than the chip they contain. For example, TI offers the NanoStar package, which is about 70% smaller (1.4 by 0.9 by 0.5 mm) than a standard SC-70 package. Fairchild's MicroPak leadless package is just slightly larger at 1.45 by 1.0 by 0.55 mm.

Designers face another challenge when it comes to the many buses proliferating on high-speed ASICs. A host of custom-designed chips and even FPGAs are designed to interface to multiple wide buses used for chip-to-chip or chip-to-backplane data transfers. Due to loading factors and system design constraints, many of these buses need buffers, latches, level translators, and other bus-oriented support functions. These devices must be low-power and fast so that they don't introduce any significant delays into the logic flow. Today, that means interface circuits with propagation delays of between 1.5 and 2 ns, and extremely low power consumption—typically a few microwatts during standby and the ability to operate from supplies ranging from 1.65 to 1.95 V.

Unlike single-gate logic, the name of the game with interface devices is density. The more buffers or latches that can be crammed into a package the better. Thus, designers have their pick of byte-wide, 16-bit, 20-bit, and even 32-bit devices. Over the next year, expect propagation delays to shrink still further and power consumption to decrease. As buses pick up speed, single-ended transceivers can no longer deal with the switching noise. As a result, designers have turned to low-voltage differential signaling. Such differential transceivers can handle data-transfer rates from a few hundred to about 800 Mbits/s.

One alternative to implementing wide, fast buses is to replace the parallel buses with several channels of high-speed serial lines via SERDES circuits. Such solutions drastically reduce chip pin counts and power consumption and allow the signals to travel on system backplanes without resorting to overly complex layout and shielding schemes.

Today, SERDES chips that handle data rates from 1.25 to 3.125 Gbits/s are readily available. Over the next year or two, serial data rates should hit 6.25 Gbits/s, thanks to new technologies like the Yellowstone and RaSer X signaling schemes (developed by Rambus). In addition to pumping up the speed, SERDES suppliers focus on lowering the power consumption per channel. Power dissipation currently ranges from about 150 to about 250 mW/channel for 3.125-Gbit/s SERDES. The goal for late 2003 is to get that dissipation level under 80 mW/channel.

Top Ten
>SERIAL INTERFACE DATA RATES will climb from today's widely available 3.125 Gbits/s to interfaces that can transfer data at rates exceeding 6 Gbits/s.

>PACKAGES FOR SINGLE-GATE LOGIC FUNCTIONS will shrink to true chip-scale packages from today's near chip-scale dimensions of about 1 by 1.5 by 0.5 mm. Bonding and contact alignment on the pc boards with such small devices will pose the big challenge for the board manufacturers. Testing the devices will also be challenging due to the handling requirements.

>BUS TRANSCEIVERS, LATCHES, and other interface circuits will continue to gain more speed, with propagation delays shrinking from current 1.5- to 2-ns levels to the 1- to 1.5-ns range. Concur-rently, the idle power consumed by the devices will drop from around 30 µW for today's multibit devices to under 20 µW.

>USE OF LOW-VOLTAGE DIFFERENTIAL SIGNALING will rise as designs increase bus clock speeds, and there's greater demand for the noise immunity delivered by differential signals.

>MULTICHANNEL LVDS INTERFACE CHIPS WILL HANDLE data transfer speeds of up to around 800 Mbits/s—about a 25% improvement over the previously available mainstream devices. This will allow designers to build faster systems without resorting to complex multilayer pc boards that have many internal ground planes to shield against noise.

>FALLING OPERATING SUPPLY VOLTAGE for logic circuits will further reduce the operating power consumption of chips. This will critically help battery-powered systems reduce their power consumption, thereby delivering longer battery life. Next-generation logic will be able to operate at levels below 1 V, which is down from today's 1.65- to 1.95-V operating range.

>MORE PARALLEL BUSES WILL BE CONVERTED to serial buses as high-speed SERDES building blocks—both as standalone chips and blocks of intellectual property that can be embedded in ASICs—become more widely available. The power consumption of these blocks is also a concern since many complex chips may want to incorporate dozens of these SERDES blocks. Today, power consumption is about 100 to 200 mW per channel, but the goal is to reduce that to below 80 mW in the next 12 months and lower still in 2004.

>SINGLE-GATE LOGIC BUILDING BLOCKS will get more play in portable systems. These nearly microscopically packaged logic functions enable designers to place them exactly where necessary, which simplifies board layout and improves circuit performance. New packaging technologies will further help reduce the chip footprint, allowing still smaller systems to be designed.

>SINGLE-GATE LOGIC FAMILIES will grow with vendors offering new logic functions and multiple speed grades. Function options now span a wide range, from basic gates and flip-flops to buffers/drivers, analog switches, Schmitt triggers, and more. Plus, multiple families with different I/O characteristics will be on the market. Designers can already pick from AHC/T, AUC, LVC, and HC/T families.

>PRICES FOR STANDARD LOGIC FUNCTIONS will plummet further due to competition with ASICs and programmable logic devices, which have been "swallowing" most discrete logic functions found on the system boards.

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