Electronic Design

Digital ICs/DSP: FPGA-Based DSP Offload Engine Accelerates Data Movement

A preconfigured FPGA-based system-on-a-chip takes aim at real-time signal-processing solutions. The CoSine architecture and internal connectivity is optimized for input data to flow through pipelined, parallelized operations in a user-programmable logic (UPL) block, with results sent using DMA transfers to conventional downstream DSP compute nodes. Able to bridge two high-speed interfaces (Serial RapidIO, PCI-X, or PCI Express), the CoSine solution enables noncontentious access to a UPL block and a quad-data-rate SRAM controller. Implemented on a Xilinx Virtex II Pro FPGA, it offloads computationally intensive functions from conventional DSPs to increase overall system performance while reducing system cost, power, and complexity. The development toolkit, which is priced at $20,000, initially includes an ATCA board with the preconfigured FPGA, up to 8 Gbytes of double-data-rate SDRAM, and demo software and tools.

Micro Memory LLC
www.micromemory.com

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