If you haven't already worked on a design project with engineers based halfway around the world, it's only a matter of time.
Driven by the relentless march of Moore's Law and the need to reduce cost to complete large chip-development programs on time, multisite design teams are rapidly becoming the norm in the semiconductor industry.
In a very difficult and competitive semiconductor business climate, companies look for any advantage out there. Vertically integrated companies are virtually extinct, which has led to highly fragmented design chains. Databases are ballooning and getting more complex. At the same time, everyone is trying to shorten product development cycles.
Time-to-market demands now require more efficient, more predictable design results. Finding enough people—the right people—to create these new function blocks and make them work together, all in a timely and competitive fashion, is the perpetual challenge.
As the industry transitions from 0.18 µm to an even more demanding 0.13-µm technology, the potential for delay increases by at least a third. Only about half of the chips in the 0.13-µm process arrive within required design schedules, according to research by International Business Strategies (IBS). Of the chips that fall behind, about 50% are well behind schedule. Companies that can't beat these design rollout numbers will very likely lose out to companies that can. What's a semiconductor company to do?
ENTER DISTRIBUTED DESIGN TEAMS
Hiring low-cost offshore talent is now commonplace in developing widely dispersed design teams. During the boom years of the late 1990s, everyone searched worldwide for engineers. Many were located in the U.K., Israel, and Asia. Another region, India, always a stronghold for information technology (IT), has moved more aggressively into application and software development.
"We're seeing the establishment of very large design and development teams in the lower-cost areas, particularly by the larger multinationals," says Christopher Tice, senior vice president and general manager of Cadence Systems Design's Verification Acceleration Group. "There's also a lot of work going to Israel—not to reduce development cost, but to take advantage of the work of skilled and experienced engineers."
Another trend, says Tice, is the consolidation of functions into systems-on-a-chip (SoCs)—so much so that the traditional lines between software, digital logic, analog circuits, and pc-board design are becoming more blurred.
Semiconductors are now being driven primarily by software. Typical SoCs have more software than hardware content, and the percentage of software content is growing.
"It has become far more important that you don't sample on first silicon anymore. You sample on first software," says Tice. Plus, the software teams are split off from the hardware group, often in a different location, and maybe even at a different company.
A recent study by the Gantry Group LLC, which conducts technology impact analysis for industry companies, shows that design management difficulties are increasing as SoC designs give way to even more complex mixed-signal technology.
To help make its point, it quotes Cadence Design Systems, which states that more than 20% of SoCs are mixed-signal, and projects that over 70% of all SoC products will be mixed-signal devices by 2006. The result of these convergence trends—hardware-software, digital-analog, and silicon-package-boards—requires previously separate design teams to work much more closely than before.
To accommodate the parallel development of intellectual property (IP), the design chains building these products have become multilayered networks of geographically distributed suppliers. While good in theory, Gantry says that working in different time zones can make this strategy a nightmare. But with the development of new multiteam design and development tools, design-chain performance may be the primary competitive differentiation.
"Design chains," the firm says, "have become as important, if not more so, than technology innovation, since it is the design chain's efficiency that governs time-to-market." (According to IBS, a 12-month delay can result in revenue reduction of 33%.)
Clearly, cost is a key motivator in new chip design. Where designing a 0.35-µm device cost at least $2 million, the Fabless Semiconductor Association says the bill jumped to more than $13 million for 0.09-µm versions (see the figure). Willem Roelandts, chairman and CEO of Xilinx and chairman of the FSA, says these costs assume that much design and verification can be done in low labor-rate geographies.
Speaking to the International Symposium on Semiconductor Manufacturing (ISSM) recently, Roelandts noted that design and verification of complex ICs now accounts for 80% of total design cost. "Design and process costs are escalating to the point where the intended application can't support the build cost," he said. "The result is that IC vendors are having greater difficulty amortizing these costs to achieve profitability."
Enhancing, or perhaps aggravating, the process is that more companies are graduating from doing some portion of the work—say, software applications—to forming and leading large-scale design teams. In fact, Cadence put together its own distributed design project team to develop Paladium, a verification/acceleration system now being used to support remote, multi-user designers simultaneously.
The Cadence program was developed in four different sites, including San Jose and India. "Talent is critical in creating the system," notes Tice. "And as I add people to my team, I'm looking for skilled workers. But I'm also always looking at economic issues, and that's what most companies look at. You have to be cost competitive."
One of the biggest cost drivers at the moment is consumer electronics, particularly wireless applications. For example, each new generation of cellular phone and PDA (which seem to be hitting retailers' shelves at an ever increasing pace) requires a new level of complexity and functionality—all consolidated into a single-chip footprint.
LOTS OF FILES
From a purely designer point of view, everything has become more complicated. "There are lots of files, lots of different versions, lots of people to deal with," says Trent Poltronetti, the marketing director of Synchronicity, which offers a suite of products that help manage team-design projects. "It gets to the point where you need some infrastructure in place to manage all the data."
Keeping track of where the pieces come from and how to integrate them pales in comparison to the challenge engineers faced 10 to 15 years ago when most work took place at one location. Then, decisions about what to do and how to do it came fairly easily. "The notion of IP then was to walk down the hall to get it from a coworker," says Tice.
It has reached the point where semiconductor companies must use some kind of tool to manage and optimize their design chain. "Our number one competitor on the chip design side," says Poltronetti, "is home-grown solutions. It runs between version-control shareware and lots of custom-written scripts. You can get away with that for a while, but then it starts to turn into a big development project of its own."
A modern, large chip-development program can easily generate 100,000 files, of which the design team may actually need just 20,000. The rest are usually iterations—intermediate steps done repeatedly until it comes out right—one function block at a time. "Even if you generate only 10,000 in files, who could keep all that straight in their head?" asks Poltronetti.
Widely dispersed design centers also help support regional OEMs and offshore original design manufacturers (ODMs), and they help win regional business. In just the past few months, Kyocera Wireless Corp. formed Kyocera Wireless India Pvt. Ltd. in Bangalore to supplement its wireless design activities in Japan and the U.S. In September, Anadigics opened a new application center in Taiwan to facilitate its customer RF design process and shorten time-to-market for wireless and broadband end products. (Anadigics also has design centers in Texas and Denmark.)
This past September, Agere Systems set up a new design center in Australia for its next-generation wireless technology development. The center will focus on silicon and systems development for third-generation (WCDMA/UMTS) communications standards, as well as future standards like High-Speed Downlink Packet Access (HSDPA). The new center complements Agere's other design operations in Germany, England, and Allentown, Pa.
TOOLS OF THE TRADE
A number of tools have been developed to manage the distributed team-design process. Among them are Synchronicity's ProjectSync, which helps manage projects and facilitates communications between designers and the process flow, and DesignSync for managing data associated with design projects.
Another one of Synchronicity's tools is the Developer Suite design collaboration and management product, which essentially connects engineers into design teams. This tool runs from $3000 to $6000 per user. Publisher Suite, which starts at $100,000 for a departmental reuse solution, can reach $750,000 for a full-blown IP distribution and support system.
Cost is often a function of the number of users and features in the system. Analysis conducted by Synchronicity last year offers an example of the return-on-investment that customers can expect from its Developer Suite on design processes, with average industry inputs:
- Average number of engineers per project = 50
- Average project length = 12 months
- Annual loaded engineer cost = $125,000
- Average re-spin cost = $192,000
- Configuration errors = 15%
- Expected revenue = $32,744,625
- Development margin = 20%
Telelogic, another design tool vendor, has focused on software-development support. Its CM Strategy DCM, a distributed change-control management tool, aims at widely dispersed designers who work under the same change-control system.
Cimmetry Systems' AutoVue and AutoVue Professional enables designers to mark up their documents, save them in different files for future revisions, define multiple markup layers, and consolidate the files once they are edited. Oridus provides a secure Web-based visualization system for back-end IC design, called SpaceCruiser. It supports multiple users and provides drawing annotation tools to facilitate communications between designers. Another Oridus product, Silicon-SpaceCruiser, enables users to view the place-and-route database. There's also a DWG-SpaceCruiser for viewing IC packaging designs and CAD drawings.
Design View from Mentor Graphics is a parts-acquisition management system. Other design management tools by Mentor include HDL Designer, HDL Pilot, HDL Detective, and HDL Author. These focus on specific aspects of design data, reuse, cost control, analysis, visualization, and documentation control.
In October, Agilent Technologies introduced its RF Design Environment wireless test benches, with system-level wireless signal sources and standards measurements from Cadence Design's Virtuoso custom design platform. Today, system-level verification of circuit-level designs is performed late in the development cycle.
The frequent use of unconnected tools to perform design verification increases risk and costs, potentially creating delays in development. According to Agilent, the company's new test benches enable communications engineers to boost their productivity and speed product development.
Some of these companies also offer highly customized products, or custom versions of their products, either of which can raise the price of the system.
All of these systems seem to get high marks from users, once their design teams get on board with them. For instance, Xilinx uses Oridus' SpaceCruiser. "We quickly established secure Web collaboration sessions between our Silicon Valley headquarters and remote sites, including our office in Ireland," says Liz Abe-Meredith, collaboration manager at Xilinx. Because the technology runs cross-platform, she notes, engineers using PCs can easily communicate with engineers on UNIX machines and vice versa.
Fairchild Semiconductor uses in-house process design kits (PDKs), along with Synchronicity's DesignSync to automate and streamline its process. Each PDK contains thousands of lines of skill code, verification code, model decks for two to three different simulation tools, process rules, several libraries of primitive and higher-level library cell views, and more. "Managing this data for over a dozen different processes was a significant challenge," says Harry Milliken Jr., a Fairchild staff CAD engineer.
To use the PDK, Fairchild implements a project-creation tool, which lets designers select a process and PDK release. "The release we use is normally the latest one, but sometimes it is advantageous to use an older release, such as when updating a design restored from an archive," says Milliken. The process and release names are stored in environment variables that are also referenced by the cds.lib files to point to the correct PDK release. Releases can be updated by simply changing the content of these variables.
Milliken says the biggest problem initially is getting users with no experience in using revision control tools to develop the discipline to use the tools and interfaces and do the check-out/check-in procedures every time.
"To the undisciplined user, the temptation to operate directly on a file and bypass the revision control mechanism may be great, especially when deadlines are approaching," he says. However, he adds that using a third-party tool for design data management and revision control has proven itself in greatly reduced errors, improved overall productivity, and shorter cycle times.
A DESIGN ALLIANCE
Chartered Semiconductor Manufacturing is taking a different tack in design optimization. Hoping to develop common design solutions for nanotechnology platforms, Chartered formed the NanoAccess Alliance in collaboration with more than 15 third-party companies. The alliance's goal is to provide extensive design support for 90-nm SoC technologies.
Design deliverables will initially focus on standard cell libraries and I/O components from Artisan Components, Synopsys, and Virage Logic; embedded memories from Artisan, MoSys, Synopsys, and Virage Logic; and EDA technology files from Cadence, Mentor Graphics, and Synopsys. The focus is on prequalifying 90-nm designs for earlier silicon validation while lowering the production risks of leading-edge ICs and SoC devices. Major design deliverables are set to be validated by early next year, in advance of 90-nm design starts.
From a purely competitive point of view, little has changed. One exception (as Cadence has pointed out) is that as supply-chain optimization became the focus for manufacturing executives in the 1990s, design-chain optimization will be the critical focus for engineering executives in this decade.
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Cadence Design Systems
Chartered Semiconductor Manufacturing
Gantry Group LLC