Everyone knows that chips, no matter how complex or well designed, don't exist in a vacuum. Neither are they designed and then tossed in a drawer. Rather, they exist as part of a system. The silicon must be interfaced to some kind of package, which, in turn, is attached to a pc board.
That chain of interconnects—chip through package to pc board—is itself a complex system, with chains of interactions that can ripple back, forth, under, and around each other. Design processes for each of these elements have been refined and optimized substantially to meet the demands of shrinking silicon, power consumption, and signaling speeds. The natural evolution from this point, then, is to look deeper into those design processes and find ways to tame those complex interactions.
In this article, we'll examine some of the fundamental aspects of chip/package/board co-design from various perspectives, including signal integrity, power integrity, thermal issues, and mechanical concerns. We'll also consider the cases of FPGAs and the emerging system-in package (SiP) concept.
WHY CO-DESIGN?
The main objective when
approaching the design of chip, package, and pc board as
a system is, of course, to ensure that the end result works
as expected when assembled and powered up. The best
way to do that is to design, analyze, and verify them all concurrently (Fig. 1).
Until recently, IC, package, and board design was approached in a sequential fashion, with each being "thrown over the wall" to the next stage of system integration (Fig. 2). In this process, each stage in the process acts as a gate. Detailed package design is delayed until the IC footprint is available, and pc board design is delayed until the package footprint is available. The result can, and often has, been a significant hit in terms of system performance, design-cycle length, and end-product cost.
A look at the complex nature of the interface between silicon, package, and board can illuminate some of the reasons why co-design can help (Fig. 3). In this example of an FPGA die, we see the power-delivery network represented in an equivalent-circuit form. Within the blue-shaded box is the FPGA silicon and its package. A given I/O bank may carry upward of 100 drivers within a die, which can switch among many of those I/Os simultaneously. What often results is simultaneous switching noise (SSN).
In this example, the die is connected to the package by means of flip-chip C4 solder bumps, which are represented by an inductance. Signals travel from the die to the ball locations through transmission lines.
Package power planes bring power into the chip, and ground planes provide a return path for both power and signals. Finally, all signals, power, and ground traces for the package are connected to the pc board by means of solder balls.
Outside of the blue-shaded box is the remainder of the system. Each pc-board pad for the surface-mounted devices, such as the FPGA, has an associated via to carry signals to buried board layers. The pc-board vias may also connect with power or ground planes within the board's layer stack up. Typically, transmission lines may also be at any level within that pc-board stackup. Further, the power-delivery network itself can actually reside at any level within the board.
THE POWER PERSPECTIVE
Unless power integrity is achieved from silicon to board and back again, performance will suffer. One can look from a number of perspectives when it comes to power integrity (Figs. 4a and
4b). The overarching issue, of course, is that without reliable power at all three levels—board, package, and chip—
performance will suffer. At all three levels, the goal is to
provide a low-impedance and low-noise path for power as
well as a return path to ground.
At one end of the power-integrity chain is the voltage regulator module (VRM) on the pc board. At the VRM, you'll typically want an R-L-C network shunting to ground. You'll also need a large capacitor shunting dc down to ground so that any unwanted transient behavior on the board at the VRM's operating frequency is shunted to ground.
The next step in the power-integrity chain is the pc board itself. On the board, designers typically use the same kinds of techniques using capacitors shunting transients to ground. These are called decoupling capacitors, or decaps. They'll often go a long way toward mitigating voltage-noise problems that can result in I/Os switching incorrectly.
There are a couple of ways to approach the use of decaps. Too often, designers err by liberally sprinkling decaps all over their pc boards, assuming that this will give them a reliable low-impedance path to ground everywhere. This may or may not be true, but what is fact is that these decaps take up space and cost money. It's a good idea to use voltage-noise analysis tools to help determine where decaps are best positioned (Fig. 5).
At board level, designers should remember that a given amount of capacitance exists between the power and ground planes in the board itself. Across the dielectric layer between those planes, there's a large capacitor that can provide emergency current at certain high power frequencies.
When it comes to the IC package, it's become popular to integrate decaps within the laminate structures of the package itself. Xilinx uses this technique in its new Virtex-5 FPGAs.
Overall, ensuring that a power-delivery network is reliable would involve using decoupling capacitances of various sizes, with associated inductances, to create tuned circuits to handle noise at all frequencies of interest.
Between package and IC, designers want to avoid simplifying assumptions, such as assuming an ideal voltage source at the chip's pads. The same can be said for assumptions of ideal power and ground layers. Analyses must account for the complexities of the power-distribution system as well as coupling effects in the package substrate that may manifest themselves at various locations on the chip.
Yet in power-integrity simulation work, it can be helpful and a time-saver to simplify and/or ignore structures that aren't germane to the analysis. Generally, today's simulation tools will offer guidance in this and other respects.
For simulation, there's a basic, but crucial, principle to observe: structures that are large compared to the wavelength of the signal they carry probably need more investigation. Vias, which look small in electrical terms, often can be modeled simply or even ignored. But as frequencies rise, those structures look larger electrically, so models should be more detailed. With more systems running at frequencies in the hundreds of megahertz or at gigabit rates (as with serializers/ deserialziers), this is an aspect of simulation that needs attention.
KEEPING SIGNALS CLEAN
While power-integrity
analysis begins at the board and ends at the IC, signal-integrity analysis runs in the reverse direction. For signal integrity, analysis often is best begun at
the IC, performed through the package,
and carried into the pc board.
Classic signal-integrity issues are becoming a greater concern in package design, especially as timing margins shrink and packages expand. The situation is exacerbated by packaging designers' penchant for very stringent physical rules, namely maintain differential impedances and eliminate reflections and discontinuities in signal paths.
To save pins on boards and in packages, designers increasingly turn to high-speed serial interfaces. Often, boards are implemented with differential-pair schemes. This does indeed save on pin counts and decrease overall costs. However, the differential pairs need to be clocked at significantly higher rates to get the same overall throughput. This adds a level of complexity on the design side.
One difficult task is the overall analysis of IC parasitics with package and board parasitics to analyze the overall system timing. With today's ICs requiring lower voltages, a small drop in supply voltage can mean significantly eroded I/O performance. This underscores the link between power integrity and signal integrity.
Another issue to consider involves periphery limits on I/Os. With shrinks in process technology, the IC die may get smaller for the same amount of functionality. But because of the requirements for high-voltage I/O transistors, the periphery of the die doesn't shrink as much. The result is a condition known as periphery-limited layout.
When you find yourself periphery-limited with an IC layout, realize that you don't need power and ground pads at the periphery, but rather only signal pads. However, tradeoffs occur in terms of signal integrity. A periphery-limited situation calls for a careful floor planning approach with regard to I/Os so that a minimum number of cells is used. Moreover, you'll want to be sure that ringing is controlled and that overshoot and undershoot don't exceed limits and cause false signals on the receiver side.
Before the chip and package are built, you'll want to examine ringing and reflections in signal paths, visualizing and analyzing these characteristics through simulation (see "Best Practices For Signal Integrity"). Overall, designers are well served if they try to avoid doing I/O floor planning for an IC in isolation. It's much better to tackle this design aspect in context of the IC's package. Once the IC leaves the fab for packaging, it's too late to solve the I/O issues. They've got to be solved as early as possible.
THE QUESTION OF SIPS
What happens when the system is the package?
More frequently, designers are turning to
the packaging technique known as system in-package (SiP) to solve integration issues
as well as save space in consumer electronics (Fig. 6).
SiPs can include stacked die, extremely dense wire bonding, and high-density interconnects and microvias that fan out from dense ICs to reach the substrate for routing to pc-board pads. As in any IC packaging, SiPs typically contain a large number of passive components, which are sometimes buried within the substrate instead of having them take up space on top.
Many thermal concerns surface with SiPs. In addition to buried passives, SiPs often will entail active elements buried within dielectric layers. It's critical to carefully consider the positioning of vias in SiPs, mostly because the vias exhibit higher thermal conductivity than the substrate material.