Electronic Design

EDA Roundup

Enhanced formal verification is the domain of Cadence's Encounter Conformal 5.0. The upgraded tool helps ensure that tapeouts accurately reflect design intent. The tool now extends equivalency checking to FPGA prototypes through the Synplicity FPGA design flow to Xilinx devices. Support for Altera parts will follow. Conformal 5.0 also offers formal verification of clock-domain crossings. Other enhancements include SystemVerilog support, complex datapath verification, and across-the-board capacity and speed improvements for equivalence checking. Conformal 5.0 time-based licenses start at $80,000. Visit www.cadence.com for more information.

Increased model interoperability and reusability will result from updated Open Core Protocol (OCP) 2.0-compliant transactional models implemented in SystemC. The models standardize the way in which OCP-based communication is modeled at various abstraction levels. The updated channel models include a speed-optimized transaction layer 2 (TL2) channel that's up to 100% faster than the previous version. The new release also includes an OCP monitor and layer adapters. Both are available only to Open Core Protocol-International Partnership (OCP-IP) members. Channel models are available to members and nonmembers. For more details and membership information, visit www.ocpip.org.

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