In 1990, the IEEE ratified the 1149.1 standard known as boundary scan. Developed by the Joint Task Action Group (JTAG), it was created to help solve the overwhelming testing problems caused by ever-increasing larger-scale ICs and densely packed multilayer printed-circuit boards (PCBs).
The old “bed of nails” method of testing PCBs no longer worked as well, and the inaccessible circuits and even pins on ICs made testing difficult if not impossible. With boundary scan, IC and board manufacturers could provide fully automated testing.
The standard has been regularly updated over the years, and a whole infrastructure of hardware and software manufacturers has emerged to support testing efforts. Thanks to recent changes, the standard is part of embedded design platforms. Boundary scan now lies at the heart of a new test and measurement approach called embedded instrumentation.
WHERE JTAG FITSITS IN
In the past, the board would have gone directly to a functional test, where it would be hooked up to power and stimulation signals to see if it worked as designed (Fig. 1). The test would be run at normal design frequencies and speeds. Such a test was performed on a bed-of-nails type of in-circuit tester (ICT). Defects were discovered and repaired.
However, years of test experience have shown that most failures are structural. Some statistics say that more than 99% of all faults lie not with bad ICs or design errors, but with PCB and solder defects such as unsoldered joints, cold solder joints, lifted pads, bridged solder connections, reversed parts, and other physical problems. That’s why most complex boards go through testing that detects such structural problems before the functional ICT.
For example, after the assembly of the complex PCB, a first step is visual inspection. An engineer may manually and visually look at the board to see if all of the parts are there and that they’re oriented properly and soldered correctly. This step may also include optical machine-vision inspection and/or X-ray inspection. Both are useful in detecting initial faults, including poor or missing solder connections.
A structural test is next. This is where boundary scan comes in. It provides a way to do a thorough test for opens, shorts, and missing connections, as well as bad solder connections not identified by other means. With boundary scan, this testing is automated with problem areas identified to make quick repairs and corrections.
After that, the usual functional testing occurs. This continues with ICTs or the bed-of-nails test heads that make contact with the board’s copper and solder connections to provide the test signals and measurements. After functional testing and repair, overall system testing is performed to conclude the process. Such system tests involve environmental evaluation as well as software and configuration processes.
JTAG STANDARD OVERVIEW
The basic idea behind boundary scan is that because most points in an IC or on some PCBs are inaccessible, designers can build in test/access circuitry that will allow an engineer to read the status of a specific node or stimulate a node with an external signal.
Today, many (if not most) large-scale ICs, ball-grid arrays (BGAs), systems-on-a-chip (SoCs), ASICs, FPGAs, and multichip modules have boundary-scan circuits built in. High-density PCBs with multiple layers also represent a test problem. The concept is to build in a large number of these test access points so a complete circuit or part thereof can be tested externally.
Figure 2 shows the essential boundary-scan architecture. The block of logic in the IC to be tested is connected to multiple boundary-scan cells. The cells are created along with the IC circuitry when the chip is fabricated. Each cell can monitor or stimulate one point in the circuitry. With its flip-flops and multiplexers, the cell can be used for either parallel-in/parallel-out or serial-in/serial-out operations (Fig. 3).
The cells are then linked serially to form a long shift register whose serial input, designated Test Data Input (TDI), and Test Data Output (TDO) serial-output ports become the basic I/O of a JTAG interface. The shift register is stepped by an external Test Clock (TCK). To stimulate the circuit, test bits are shifted in. This is called a test vector.
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To monitor the circuit under test, the status of the circuits is sampled and stored in the shift register. Then it’s shifted out serially where software is used to compare the test pattern with an expected pattern. When multiple JTAG-enabled chips are used on a PCB, the serial data I/O of each chip is daisy-chained with all others, and the final result appears at the single JTAG interface.
The TCK rate isn’t related to any system clock. TCK is a separate clock typically in the 10- to 100-MHz range; 10-, 25-, and 40-MHz rates are common.
In addition to the serial-in, serial-out and clock signals, a Test Mode Select (TMS) input is provided as well as an optional Test Reset pin (TRST). The TMS, TCK, and TRST signals are applied to a 16-state finite state machine called the test access port (TAP) controller. Along with external binary instructions, it controls all of the possible boundary-scan functions.
The instruction register in Figure 2 decodes one of the four mandatory instructions—Extest, Bypass, Sample, and Preload (see the table). Optional instructions are Intest, Idcode, Usercode, Runbist, Clamp and HighZ.
When Idcode is executed, the device identification code permanently stored in the 32-bit Identification register is scanned out. When the Bypass instruction is run, the TDI is connected to the TDO via a 1-bit bypass register. This shortens the serial boundary register when a segment of the test is no longer needed. In some chips that provide built-in self test (BIST) circuitry, there’s also a result data register. This register’s output can be shifted out using the Runbist command.
The JTAG interface I/O lines are usually connected to an interface card or box connected to a PC. The interface box contains memory that’s loaded with the test vector bits. It also stores intermediate results and communicates with the PC where the test software resides. Commercial software provides a way to get data into and out of the device or PCB as the test requires.
Part of the JTAG standard defines the Boundary Scan Description Language (BSDL), which defines all boundary-scan features, capabilities, and logic built into each IC. The chip vendor supplies the BSDL file for each IC it makes.
The test software requires two things for a PCB test: the BSDL files for each chip on the board, and the board netlist that defines the connections on the PCB. With this data, the test software program-generation function creates the basic test procedure and sequence. It can then execute the test. After that, the software supplies a report of the results.
As mentioned earlier, the original JTAG standard has been updated and added to over the years. Below is a summary of the current IEEE standard designations:
• IEEE 1149.1: The original standard that has been revised and updated several times
• IEEE 1149.4: Analog boundary scan for mixed-signal devices; adds two additional pins for analog-in and analog-out testing; not widely used
• IEEE 1149.6: AC boundary scan; a capacitive-coupled version for testing high-speed I/O such as low-voltage differential signaling (LVDS)
• IEEE 1149.7: A reduced pin-count version (five to two with multiplexing) and enhanced functionality testing
• IEEE 1532: In-system configuration; using boundary scan to program flash, embedded controller memories, complex programmable logic devices (CPLDs), and FPGAs
• IEEE P1581: Static component interconnect test, to be used for memory devices
• IEEE P1687: Access and control of embedded instrumentation that addresses testing of higher-speed, higher-density chips, boards and systems; dubbed IJTAG (internal JTAG), a standard is in the works; for more details, go to http://grouper.ieee.org/groups/xxxx, where xxxx is 1149, 1532, 1581, or 1687
The hardware and software products in the marketplace are key to successful boundary-scan application. JTAG Technogies’ JT 37x7/APC plugs into the Agilent 3070, a widely used ICT product in automatic-test-equipment (ATE) board testing (Fig. 4).
According to the company, combining both structural and functional testing as well as in-system programming in one product yields economies as well as gains in testing speed and accuracy. A rack-mount version is available for convenient integration into existing test systems.
The ultimate “secret sauce” for boundary-scan application success is the software. The PC-based tools in ASSET InterTech’s ScanWorks suite can be configured for design validation and debut in a development environment, test creation, application and diagnosis during manufacturing, flash and logic programming in processors and FPGA/CPLDs, and troubleshooting and diagnostics during field test and repair. The company also has a full range of hardware accessories to complement ScanWorks. JTAG Technology has similar software called JTAG ProVision and JTAG Visualizer.
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The original boundary-scan system was created to facilitate the production testing of high-density PCBs. It was quickly incorporated into many ICs. With boundary-scan capability in each chip, the board could be fully tested for shorts, opens, and interconnects between the ICs. Though that’s still the main use of boundary scan, other applications have emerged. Boundary scan is now widely used in product design, prototype debugging, and field service.
In product development, boundary scan is a good way to test and debug a prototype board. With its small size, multilayers, high density, BGA, and fine-pitch ICs, a complex PCB can be tested without a special in-circuit test fixture. That’s because most major ICs used today incorporate a JTAG port. This is especially true of almost every embedded controller and processor as well as most CPLDs and FPGAs.
For software debugging on specific CPUs, the JTAG interface can be used to download code from a CPU, preload registers, run a program, and then look at register and memory content to determine correct operation. JTAG is also widely employed for emulation. With the appropriate software, a test program can be built to test and debug the product.
One key role for JTAG today is programming ICs. Embedded controllers can have their internal flash programmed. Any programmable chip can be initially programmed and updated as needed with its JTAG interface. FPGAs and CPLDs can similarly be programmed and later updated as required. This allows unprogrammed chips to be installed when the PCB is being assembled, saving the extra time and cost of programming the chip before assembly. Programming can be done before the final functional testing.
Boundary scan has also found its way into field service, performing software upgrades, updating flash ROM, or reprogramming CPLDs or FPGAs. And, it can serve as the basis of a fault diagnostic feature to quickly pinpoint problems.
JTAG has additionally been called into play since design for testability (DFT) and BIST features were incorporated into the newer, more complex chips. The larger SoCs are far more difficult to test individually as well as in the final product. As a result, chip designers have been embedding extra hardware into these chips so they can test themselves. This feature significantly reduces chip test time and cost, and in many cases, it can eliminate the need for expensive ATE.
Though BIST hardware obviously increases the silicon area of the chip, it’s usually small compared to the full chip circuitry. That extra circuitry can also degrade performance, cause timing problems, and add other undesired overhead. However, being able to test the chip and system faster, and cheaper, typically outweigh these downsides.
There are several types of BIST classification, such as logic BIST and memory BIST (Fig. 5). Analog BIST isn’t as common, but there’s a growing need for analog and mixed-signal testing. A pseudo-random test-pattern generator helps create test signals for the circuit under test (CUT). The circuit’s outputs are then stored in one or more results registers that will be scanned out to be analyzed.
In some cases, the comparison to the desired result is also done on-chip, so the output is simply a pass/fail indication. In newer BIST, the inputs and outputs are put through a data compression process to significantly reduce the amount of test bits and output data to be analyzed. In larger chips with hundreds of millions of circuits, test data volume can overwhelm a test engineer, not to mention any testing equipment.
Typically, the huge test vector file is compressed and sent to the BIST circuits. Then the test bits are decompressed and used in the test. Finally, the output results are compressed or compacted before being read out. The compression provides a compact output word or signature as much as 100 times smaller, which is easier and faster to analyze.
Also, compression is used to thwart hackers who have discovered that they can steal data, encryption keys, and IP secrets by reading the scan chains. Compression essentially solves that problem. Mentor Graphics’ TestKompress is one example of such compression.
Another method of BIST implementation within a chip is to connect all flip-flops and registers serially into scan chains that can provide a way to enter test states or retrieve test results stored in the chain. A complex chip may have multiple scan chains rather than one long serial chain that could slow testing. Test vector bits are scanned into the chip, which can then be functionally tested at design speed.
At some point in the test, a capture event occurs to store the test results, which are then shifted out for comparison to the desired output. With both types of BIST, JTAG may be used to insert test bits or capture the output results in its data registers for output testing. As of yet, no standards exist on how JTAG is employed with BIST, but the IEEE 1687 effort hopes to remedy that.
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WELCOME TO EMBEDDED INSTRUMENTATION
As semiconductor feature sizes continue to shrink into the 65-nm and below range, chip density and complexity continue to increase as vendors load more onto a single chip. These smaller geometries also permit higher data rates well into the 5-GHz+ region. What’s resulted is even more difficulties in testing these chips and the boards they populate.
This problem has forced chip vendors to go beyond scan chains and JTAG to create innovative techniques to access and test the circuitry on these advanced chips. Some are proprietary to chip vendors, and some can be used in conjunction with JTAG. Collectively, these techniques are known as embedded instrumentation.
This testing problem is especially acute with the newer high-speed serial buses being deployed in most new computers and other equipment. PCI Express, Fibre Channel, 10-Gbit/s Ethernet, Serial ATA (SATA), fully buffered DIMM (FBD), and others are examples.
Considerable distortion and signal degradation occurs at speeds of 5 Gbits/s and above, even over several inches of PCB trace, making it difficult to really know what the signal looks like. Connecting a scope to such a trace even introduces further distortion. Since such traditional methods are no longer as useful, new embedded testing methods are on the drawing board.
This plan moves some or all of the testing instrument or circuit on-chip. Embedded instrumentation is an extension of BIST. It can generally be defined as any design validation, test, or debug IP embedded in a core, SoC, system-in-a-package (SiP), board, or system that can be used by design, test, or manufacturing to achieve testing, measuring, or other engineering tasks.
Because embedded instrumentation is in its infancy, there are no standards. But the IEEE 1149.1 JTAG group proposed an extension to the boundary-scan standard that will allow the JTAG TAP to manage the configuration, operation, and collection of data from this embedded instrumentation circuitry. This effort falls under the aegis of IEEE 1687, or IJTAG, too.
“When you start to scratch the surface, you see that embedded instrumentation is critical as the industry moves forward to higher speeds, smaller geometries, and greater densities,” says Glenn Woppman, president and CEO of ASSET InterTech.
“Not everyone calls it embedded instrumentation, but much of the logic that is being embedded addresses issues like design validation, test, debug, device, and board monitoring and other types of instrumentation functionality. That is what we call embedded instrumentation,” adds Woppman.
ASSET is so confident in embedded instrumentation that it has repositioned itself as a company devoted to providing open tools for embedded instrumentation. Its new motto is “Driving Embedded Instrumentation” (Fig. 6).
When you come down to it, embedded instrumentation could be considered the next evolution of the test and measurement industry. It is a generational step beyond virtual instrumentation and its modular hardware and software like National Instruments’ LabVIEW. ASSET InterTech’s ScanWorks JTAG software platform appears to be a great starting point for becoming the LabVIEW of embedded instrumentation.
Intel’s IBIST (Interconnect Built In Self Test) design validation and test architecture allows chip-to-chip interconnect testing and design validation of high-speed buses on a PCB. It’s built into Intel’s 5300 and 7300 series Quad-Core Xeon processor- based platforms used in servers. It will also be used in Intel’s next-generation Nehalem processor platforms.
IBIST uses signal-integrity analysis through margining, bit-error-rate testing (BERT), and pattern generation testing. It also uses boundary-scan test, in-system programming, and design for test. ASSET’s ScanWorks supports it.
Lots of other companies are also beginning to incorporate embedded instrumentation. For example, Altera is making its Pre-emphasis and Equalization Link Estimator (PELE) available to electronic design automation (EDA) companies like Mentor so designers can use it for signal-integrity measurements on the Stratix II GX FPGAs. DAFCA, an EDA company, allows chip designers to incorporate reconfigurable instrumentation from its IP library.
Logic Vision lets designers deploy its embedded serializer-deserializer (SERDES) loop-back solution, which characterizes the parameters that determine signal eye distortion. Maxim incorporates monitoring instruments in some of its power-management chips. And, Rambus is integrating a programmable pseudo-random-pattern-generating instrument and bit-stream comparators into I/O blocks on its memory chips.
Synopsys now offers its DesignWare Verification Library of embedded instrumentation IP. Vitesse Semiconductor has come up with a series of new transceiver and SERDES chips that incorporate its VScope waveform-viewing technology based on equalization and a unique sampling technique. Furthermore, Xilinx’s ChipScope Pro real-time debug and verification tool inserts a logic analyzer, bus analyzer, and virtual I/O instruments directly into an FPGA. Expect more news and announcements in this space in the coming months.
Laung-Terng Wang, Charles E. Stroud, Nur A. Touba, editors, System-On-Chip Test Architectures, Nanometer Design for Testability, Morgan Kaufmann Publishers, 2008.