Last year was a major turning point for the analog world. Like programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs) in the digital domain, field programmability and in-system reconfigurability finally pervaded the analog front. Several single-chip field-programmable analog arrays (FPAAs), in-system programmable filters, and analog building blocks emerged, giving system designers a new capability.
With accompanying easy-to-use CAD programs and Windows-based integrated design environments (IDEs), engineers can now define complete analog functionality on a PC screen, view the results instantly, and download the circuitry onto the associated chip by only clicking a button. Also, these programmable analog ICs can be reconfigured on-the-fly to adapt dynamically to real-time system requirements.
Gone are cumbersome pc-board layouts, passive and discrete soldering, and tedious trials and errors. According to Hans W. Klein, Lattice Semiconductor's director of mixed-signal products, "what you see is what you get" with pinpoint accuracy. Plus, the design is laid out and implemented instantaneously. Weeks of laborious design and development work is accomplished in minutes with point-and-click software.
The easy-to-use graphical Windows-based software makes programming and reconfiguration jobs look like a piece of cake, notes Shane Messerly, a senior design engineer at Inceptio Medical. This Farmington, Utah-based company makes ultra-sound imaging products. Messerly has deployed Lattice Semiconductor's in-system programmable ispPAC80 as an anti-aliasing filter in front of a 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) with a 500-kHz sampling frequency.
"Compared to a discrete solution, this is much better," he says. It offers a steep roll-off and takes only a few bypass capacitors for power supplies to complete the solution. Satisfied with the performance, designers at Inceptio Medical plan to take this programmable low-pass filter to production. While the present programmable cutoff frequency range for the device is 50 to 500 kHz, Messerly hopes to see it offer a much broader range in the future, with extensions at the lower and higher ends.
Unwrapped early last year, a single ispPAC80 chip contains all of the components required to implement almost any popular continuous-time fifth-order LPF topology with programmable gains of 1, 2, 5, and 10, and programmable cutoff frequencies from 50 to 500 kHz. Supporting it is an IDE, labeled PAC-Designer, which includes a search engine and a filter database of over 8000 configurations and a simulation tool.
The ispPAC 80 lets designers configure a desired response on a PC screen using parameters like cutoff or corner frequency (fC), ripple, roll-off, and stop-band attenuation. Upon satisfaction, the user simply downloads the filter configuration onto the chip's EEPROM memory with a button click.
Every popular response known can be implemented, including Butterworth, Bessel, Chebychev, Legendre, elliptical, Gaussian, and linear-phase types. From a single programmable device, one can obtain thousands of different responses (see "Programmable Analog IC Provides Popular Filter Responses," Electronic Design, Feb. 21, 2000, p. 66).
This programmable filter comprises a programmable-gain high-speed instrumentation amplifier, a fifth-order filter core, a buffered differential voltage output, two nonvolatile configuration memory registers, a precision voltage reference, and auto-calibration. Plus, it includes fixed resistors and variable capacitors arranged in seven arrays. Each array offers hundreds of variations in capacitor values. It has a differential signal path from input to output to guarantee high performance and signal integrity. So that engineers can configure the device when it's soldered to a pc board, it offers a digital I/O interface.
Because it eliminates external components and clocks, it's a robust device that is insensitive to component and temperature variations. This approach yields repeatable filters that can simplify a production job, Lattice Semiconductor designers claim.
Serious about changing the analog design methodology, the company has extended its in-system programmable (ISP) PLD technology to create more programmable analog parts for addressing various application needs. Presently, the portfolio includes two other programmable parts aside from the programmable filter. The ispPAC10 and ispPAC20 are aimed at designing analog front ends for data-acquisition and control applications.
Jeff Berry, a senior design engineer with Atlantek, a producer of electromechanical printers based in Wakefield, R.I., uses the ispPAC20. He has tapped this device to realize a servo current drive for a subfractional dc motor that drives ribbon in the printer. "It provides all standard analog components needed on a single chip, and it could be configured in the system using the SPI interface," he says. "The CAD tool is fairly convenient to use."
But it isn't yet perfect. For Berry's application, the capacitor values were inadequate. "For the kind of frequency response and loop-gain configuration we needed, we had to go off-chip to realize a long time-constant circuit," he notes. Despite these caveats, Atlantek is in the prototype stage with this approach and intends to take it into production soon.
Using the in-system programmable amplifier, senior electronics engineer Walt Wilson was able to quickly design programmable analog instrumentation amplifiers and filters for an analog front end of a compact telemetry system. He met the deadline for this military project undertaken by his company, Amtec, a contractor based in Huntsville, Ala. But during tests, a layout error was discovered on the circuit board, and the analog outputs were found to be on the wrong pins.
Getting back to the PAC-Designer, Wilson had reconfigured the internal routing via the analog routing pool inside of the chips and downloaded the new configuration via the JTAG port for all 16 channels of the telemetry system. He was back in business and testing resumed. Some tweaking was necessary, so he went back to his laptop and further optimized the gains and offsets for the circuitry and again downloaded the latest configuration to bring all channels within tolerance.
While the early introductions were modest in performance, integration, field programmability, and reconfigurability, the complexity is now on the rise. Lattice is preparing a new ispPAC member with higher integration, increased operating bandwidth, more flexibility, and infinite reconfigurability.
For infinite reconfiguration during system operation, Lattice has added SRAM cells to existing EEPROM cells on-chip. Jim Krebs, senior mixed-signal applications engineer, claims a designer can thereby program the chip in EEPROM as a starting configuration and then reconfigure the device infinitely during system operation using the SRAM cells, through the JTAG and SPI ports. "The SPI port and SRAM memory combination allows real-time adjustments via the microcontroller," he says. "Plus, it will offer over a 10-MHz bandwidth to lend itself for the video range."
Other features include full control over the feedback path, greater flexibility at both input and output, finer gain resolution, offset auto-calibration, power-down and standby modes, and an improved analog routing pool (Fig. 1). In short, this latest device from Lattice will integrate all essential analog front-end functions for a typical data-acquisition circuit, control loops, and 8- to 12-bit ADCs.
A new version of the PAC-Designer software is in the works, permitting adjustments during manufacturing. To compensate for other component tolerances on-board, it will let engineers adjust the chip's analog parameters in the manufacturing line, yielding higher performance and better productivity (Fig. 2). To familiarize engineers with its devices and methodology, Lattice has developed evaluation boards as well as application notes.
Another proponent of real-time programmable analog is Anadigm, formerly Anadyne Microelectronics. This U.K. startup has merged SRAM-based FPGA technology with analog cells to create an FPAA on a single chip. The first fruit of this effort is an FPAA that provides a matrix of 20 configurable analog blocks (CABs). Each CAB has an op amp, a comparator, five switched-capacitor arrays, and other support circuitry, surrounded by a programmable interconnect and I/O structure.
In addition to 20 programmable op-amp CABs, the FPAA (the AN10E40) includes an 8-bit programmable internal voltage reference and four programmable clocks, with a maximum frequency of 1 MHz. Both resources are accessible by any CAB in the array. Around the periphery of the array are 13 analog I/O cells, preconfigured to act as buffers (Fig. 3).
Common analog signal-conditioning functions—offset removal, rectifiers, gain stages, comparators, and first-order filters—can be implemented using just one CAB. More complex functions, like high-order filters, oscillators, pulse-width modulators (PWMs), and equalizers, take two or more CABs. When using 20 CABs, complex signal conditioning for multiple channels and/or signal-processing functions, such as a full PID control, can be employed with a single FPAA. Also, with the addition of external resistors and capacitors, these cells may be configured as Sallen-key filters for either output smoothing—to remove unwanted high-frequency signals resulting from the array's switched nature—or as anti-aliasing input filters.
Anadigm's FPAA also offers two uncommitted unity-gain amplifiers at the periphery, allowing the application of fourth-order Sallen-key filters (−80 dB/decade) to the key input and output signals. The chip operates from a 5-V supply. On-chip SRAM, initialized at power-up from an off-chip EEPROM or through the chip's microprocessor peripheral interface, holds the circuit's configuration.
The key to the FPAA's versatility is the accompanying CAD program, AnadigmDesigner. With its analog function library, this CAD tool allows even novice users to build systems without knowing the underlying circuit techniques, contend Anadigm's designers.
With the FPAA, no math abilities, circuit knowledge, or simulation skills are required. Moreover, building a trial circuit doesn't require breadboarding. Instead, a user simply selects the desired analog functions and enters the needed characteristics. For instance, to implement a biquad filter, a user specifies cutoff frequency, bandpass gain, and Q factor.
AnadigmDesigner offers over 50 such ready-to-use parameterizable analog functions. These include gain stages, summing amplifiers, sample-and-hold (S/H) amplifiers, high-, low-, and bandpass/stop filters, high- and low-Q filters, cosine filters, squarewave and sinewave oscillators, VCOs, full- and half-wave rectifiers, single- and dual-input comparators, dc reference voltages, limiters, peak detectors, Schmitt triggers, noninverting integrators, differentiators, and ramp and triangle waveform generators. Using this software, a designer can simply drag-and-drop necessary analog functional blocks and click a button to download the configuration onto the FPAA chip.
To allow engineers to evaluate the technology and develop working systems, Anadigm has released an evaluation board with a serial interface for PC connection. Analog circuits created with the CAD package can be easily downloaded onto the chip. The evaluation board additionally includes an 8-bit microcontroller, the HC08, which can dynamically modify the FPAA's functionality. "This feature permits the engineer to explore the concept of adapting analog performance in a software-controlled, event-driven environment," says Mike Kay, president of Anadigm.
Advanced Linear Devices (ALD) has leveraged its patented electrically programmable analog devices (EPAD) circuit-trimming technology to develop an ASIC design methodology for packing up to 50 op amps on a single CMOS die. Each op amp in this dense array can be electrically trimmed to better than 1.0 mV for high-precision applications. Initial efforts were focused on op amps. But according to John Skurla, ALD's marketing director, other functions like comparators, analog switches, and data converters can be implemented too.
For a sensor application, ALD has developed an eight-channel analog circuit using this methodology. Every channel comprises six EPAD-based op amps. Within it, each op amp serves as a building block. An on-chip multiplexer permits directing the injection or programming voltage to the right EPAD op amp. "While ALD's on-chip arrays are restricted to EPAD-based devices, the specifications can be tweaked to meet a designer's needs," Skurla asserts (see "Custom Linear Array Incorporates Up To 48 Precision Op Amps Per Chip," Electronic Design, March 19, p. 46).
Whereas some companies have demonstrated field-programmability and in-system reconfigurability in standalone analog ICs, others are bringing such programmability to system-on-a-chip (SoC) solutions. In a processor-centric SoC design, analog and I/O peripherals are normally fixed. Makers like Analog Devices, Texas Instruments, and Microchip Technology have added analog peripherals around their respective DSP/microprocessor cores to generate a complete system-level solution. But, these are primarily fixed.
As system needs continue changing rapidly with evolving standards, SoC solutions must also adapt quickly to changes in the chip's analog front end. Consequently, cost and time-to-market pressures demand new levels of flexibility and reconfigurability from SoC chips. This has motivated Cypress MicroSystems, a subsidiary of Cypress Semiconductor, to extend the proven programmable technologies of the digital world to the analog front. Combining programmable techniques with IPs and microcontroller architectures, Cypress MicroSystems has crafted a new generation of programmable SoC devices, known as PSoCs.
Toward this goal, Cypress MicroSystems has developed analog and digital building blocks called SoCblocs, which are integrated around a microcontroller core. These SoCblocs allow designers to realize analog and digital functions for a variety of embedded applications. Using multiplexers and switches, developers at Cypress MicroSystems have further interconnected these SoCblocs to create higher-level functions, labeled user modules. Subsequently, Cypress has generated a library of these modules, which include SAR ADCs, incremental ADCs, delta-sigma ADCs and DACs, programmable low-, high-, bandpass/stop filters, programmable-gain amplifiers, S/H amplifiers, waveform generators and detectors, and modulators/demodulators.
The initial launch consisted of about 40 analog and 30 digital user modules (see "Programmable SoC Delivers A New Level Of System Flexibility," Electronic Design, Nov. 20, 2000, p. 74). But the supplier intends to expand this library and enhance the resolution of the data converters. Right now, the converters in the library offer 12-bit resolution. Cypress plans to push that higher in next-generation PSoCs.
Employing the PSoC Designer, a Windows-based IDE software, a user can connect these higher-level user modules into a desired system. Using only a PC screen and icons, a user can configure and reconfigure both analog and digital arrays of the device graphically and then instantly map the system configured onto the PSoC chip by clicking an icon.
The PSoC Designer contains three subsystems; the device editor, an applications editor, and a debugger (Fig. 4). In the device editor mode, user modules are selected and interconnected, and then mapped onto the SoCblocs on-chip to realize the final PSoC microcontroller. The first PSoC family is built around the company's 8-bit M8C microcontroller core using the maker's proprietary silicon-oxide/nitride-oxide silicon (SONOS) programmable nonvolatile process, integrated with a high-volume CMOS SRAM process.
Field-programmable and in-system reconfigurable analog ICs have arrived. They will change analog design, making life easier for experienced and inexperienced designers alike.
|Suppliers Mentioned In This Report|
Advanced Linear Devices
Analog Devices Inc.
Microchip Technology Inc.
Texas Instruments Inc.
(800) 477-8924, ext. 4500