Electronic Design

FPGA Gets The Hang Of Low Power

Until recently, low-power FPGAs were about as oxymoronic as bipartisan cooperation and bug-free code. But the FPGA landscape is changing for the better as more vendors can say with a straight face that they offer low-power FPGAs without having their marketing guy laughed out of the room.

Not only that, but FPGAs also have been getting more and more design wins in battery-based portable applications in which low power consumption is paramount, such as cell phones and portable navigation devices. Combined with their inherent rapid prototyping capabilities, this makes FPGAs an attractive alternative over ASICs and ASSPs.

Rapid prototyping enables portable device vendors to keep up with the frenzied pace of innovation, where design cycles may last only a few months. FPGAs are additionally attractive because standards evolve rapidly and vendors want to offer the latest technology, such as touchdriven GUIs.

The FPGA’s leap into new territories has been made possible because many vendors have added new process technologies to attack leakage current issues. They also have lowered the core operating voltage to reduce static power consumption. And, vendors are upgrading their tools to provide feedback about power consumption and can better assist with providing lower power consumption for a given design (see the figure).

Actel has taken these steps and more to reduce power consumption with its Igloo family of FPGAs. These true (versus hybrid) flash-based devices feature considerably less power consumption than their SRAM-based counterparts. According to Actel, flash-based solutions can reduce power consumption caused by leakage current by two to four orders of magnitude. Case in point, Actel offers a device that consumes a mere 5 µW of static power, compared to the several milliamps used by SRAM-based FPGAs.

“Flash-based FPGAs also feature significantly lower (total system) dynamic power than their SRAM-based counterparts,” said Fares Mubarak, senior vice president of Actel. “Dynamic power is a function of device architecture, design tools, and operational voltage.” The Igloo family is also available in a 4- by 4-mm ball-grid array (BGA) package with a 0.4-mm ball pitch. And since the family is flash-based, no external configuration memory is required, saving additional board space.

“Smaller than a kernel of corn, the new Igloo FPGAs are an ideal solution for power-sensitive, space-constrained handheld devices such as smart phones, portable media players, secure mobile communications devices, remote sensors, security cameras, and portable medical devices,” said Mubarak.

The Igloo family offers many other power-saving innovations, such as instant on. Its Flash*Freeze mode switches between dynamic and static operating modes. Tool-based features include a power-driven (rather than timing-driven) layout. The end result: “Total power for Actel’s 1.2-V FPGAs is typically 60% lower than competing FPGA suppliers,” concluded Mubarak.

Actel has put together a list of 10 powersaving techniques (see “10 FPGA Tricks Provide Power-Saving Treats,” right). Sampling now, the Actel Igloo 15,000-gate device will be available in the second quarter for $0.99 in volume.

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