Electronic Design
FPGA Module Delivers Front Panel API Via SuperSpeed USB 3.0

FPGA Module Delivers Front Panel API Via SuperSpeed USB 3.0

Opal Kelly has been delivering compact FPGA modules for quite awhile (see External FPGA Module Uses PCI Express Host Link). The XEM6310 series (Fig. 1) is their latest offering. The board sports a Xilinx Spartan 6 FPGA plus a SuperSpeed USB 3.0 interface. The FPGA can be an XC6SLX45 (45K LUTs) or an XC6SLX150 (150K LUTs). The USB link provides a very high speed interface with transfer rates exceeding 300Mbyte/s for programming as well as communication with a host device like a PC. A pair of Samtec connectors provide access to the FPGA I/O.

74549_fig1smA_XEM6310

Figure 1. Opal Kelly's XEM6310 module provides access to a Xilinx via USB 3.0

The XEM6310 module (Fig. 2) also contains a microcontroller but it is not one that a developer programs. Instead, it provides a link between the FPGA and the host. The link is used for programming the FPGA as well as interfacing the FPGA to the host simplifying the development process because Opal Kelly adds support on the host as well as in the FPGA.

74549_fig2_XEM6310-Block-Diagram
74549_fig2_XEM6310-Block-Diagram

Figure 2. XEM6310 USB 3.0 FPGA Module exposes the FPGA via a pair of Samtec connectors. The FPGA also has dedicated serial flash and DRAM.

The module contains two external, serial flash chips. One is for the USB micro that can be used to program the RAM-based FPGA when the system is turned on. The other is accessible to the FPGA and can be used for the application installed in the FPGA. There is also 128 megabytes of DDR2 DRAM for the FPGA to use as well.

The Opal Kelly FrontPanel support (Fig. 3) simplifies a developers job where the FPGA needs to interact with other devices such as applications running on a PC. The host PC provides an API to access and control interfaces on the FPGA. Opal Kelly's HDL must be included in the FPGA project but it provides access to the internals of the FPGA.

74549_fig3_Front-Panel-UI

Figure 3. Opal Kelly provides the FrontPanel software on the host and HDL for the FPGA to tie the FPGA application to a programming running on the host PC.

This interface can be used for development and debugging or it can be used to implement part of an application such as a control panel user interface (Fig. 4).

74549_fig4sm

Figure 4. Opal Kelly can provide a front panel-style user interface on the host PC that is driven by information in the FPGA.

The Opal Kelly API can be used to develop custom applications tied to the FPGA. There is also support for National Instrument's LabView (Fig. 5). This utilizes the FrontPanel API but allows developers to simply use LabView for the host application. LabView can also be used to create the FPGA design as well although that is a different tool flow. The standard FPGA development environment uses Xilinx's ISE or the new Xilinx Vivado (see FPGA Design Suite Generates Global Minimum Layout).

74549_fig5sm_LabView
74549_fig5sm_LabView

Figure 5. The LabView SDK uses the FrontPanel API to interface to National Instrument's LabView graphical development environment.

The XEM6310 USB interface employs a 32-bit API for the register bridge versus the 16-bit interface used with prior platforms. This simplifies interfacing to 32-bit micros since the final host does not have to be an x86 platform. The system supports multiple configuration profiles although usually a single profile is needed for most applications.

Opal Kelly makes the job of working with FPGAs significantly easier. The on-board switching power supplies eliminate the design chore for developers. The modules are designed for deployment for small to midrange markets. The design can be turned into a custom board for high volume applications.

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