Electronic Design

FPGA Q&A: Xilinx

Electronic Design held a series of Q&A sessions with several major FPGA companies. Here, our roundtable discussion with Xilinx included Frederic Rivoallon, synthesis methodology manager; Philippe Garrault, senior technical marketing engineer; Chris Stinson, senior manager, Product Applications Engineering; Mike Frasier, director of engineering, IP Solutions; Mark Goosman, product marketing manager, Programmable Digital Systems; and Steve Sharp, senior manager, Competitive Programs.

Question: What are the top five to 10 issues your applications engineers deal with on an ongoing basis? How are the problems handled at the customer level, and how are they addressed by the company as a whole?

Answer: If we look at the technical-support case data, some of the top challenges for customers include:

Configuration: This accounts for about 16% of inquiries. We are actively listening to our customers and incorporating their feedback, questions, and issues into the tools and documentation. We are also expanding our Web content to enable customers to quickly find information they need.

Embedded design: This accounts for about 13% of inquiries. Close partnership between applications and development enable quick identification and resolution of issues, as well as driving customer feedback into future requirements and releases.

The top issues relating to the ISE design tools are related to mapping, place-and-route, Project Navigator, and the XST Xilinx Synthesis tool.

Additional areas challenging our customers include memory interfaces, IP integration, and power management.

In addition to providing a domain-optimized silicon platform, Xilinx has taken a solutions-optimized approach to its product portfolio. We offer a comprehensive array of application- and market-specific libraries of reference designs, kits, IP, and software tools designed to shorten development cycles and reduce time-to-market.

Question: What flow do you suggest your customers follow when starting a new FPGA design?

Answer: Customers can use third-party tools, such as XST, Precision, or Synplify, for synthesis, and then use Xilinx ISE 9.1i for place and route. For simulation, customers can use either ModelSim, NC Sim, or VCS. They should always enter timing constraints for synthesis.

Question: What is normally suggested to your customers regarding the handling I/O signal assignments? In what order do you suggest the various signals types be assigned? (That is, start with VREF, move to high-speed I/O, and so on.)

Answer: FPGA I/O assignment must reconcile several times, sometimes contradicting constraints:

  • Constraints from the PCB, such as escape routes, board space, and congestion; and signal-integrity effects (length match, max attenuation, max via, etc.)
  • Constraints from the FPGA architecture (I/O baking rules, SSO, clocking rules, etc.)
  • Constraints from the customer design (timing, location of the logic source/destination within the device, etc.)

Each FPGA architecture/customer design combination will have its own constraints environment. Giving general rules is no easy task. Typically, you first want to loc FPGA pins that have the tightest constraints. A typical order for pin assignment might be:

  1. Input global/regional clocks, FPGA configuration pins
  2. MGT (SERDES), high-speed single-ended (memory/CPU interface), differential signals, reserve multipurpose pins that cannot be used as user I/O because of the particular customer design (DCI reference voltages, input reference voltage)
  3. Other sets of pins (buses) that require grouping into adjacent package pins on the FPGA for internal timing or pc-board (PCB) layout
  4. Finally, slow signals (reset, etc.)

I/O assignment can be done in multiple ways—ISE (PACE, Floorplan Editor), third-party vendors (Mentor I/O Designer), PlanAhead or even Excel spreadsheet. Useful resources would be:

Question: What approach do you suggest to your customers when dealing with incompatible I/O standards, different voltage references, and other issues with respect to bank or region compatibility?

Answer: The best way is to draw two spreadsheets.

  • List all design I/Os and their electrical properties and preferred location on the package. Then, create classes/groups of signals sharing compatible I/O power/reference voltage.
  • List all of the device user I/O and their properties. You can sort that table by I/O bank, since all pins within an I/O bank share the same power and reference source.

Then, filter out all dedicated or already assigned I/Os from both spreadsheets. By filtering the user signal by class, it becomes easy to match your I/Os with the different I/O banks. Some useful resources for this topic would be:

Question: How do you tell your customers to prepare for a migration path to another FPGA, a structured ASIC, or ASIC?

Answer: Given the length of time necessary to do the re-verification and test-vector generation for a structured ASIC or ASIC conversion, the best alternative toward reducing FPGA-design cost is to use the Xilinx EasyPath solution. It leverages the same FPGA silicon, but uses a different test methodology to create a design-specific testing methodology that increases yield and lowers cost. In this migration, there’s no need to do special preparation or eliminate the use of any FPGA features because they will all be available on the EasyPath implementation.

For users doing ASIC prototyping with larger Xilinx FPGAs, the usual way of easing the transition to the eventual ASIC is to keep device-dependant functions (such as memory) in their own unique hierarchy modules. Therefore, they can be replaced with the ASIC versions of those functions later. Of course, the downside of this methodology is that the user gives up the ability to make full use of embedded hard blocks (e.g., complex block RAMs, DSP/multiplier blocks, digital clock managers, Ethernet MACs, and PCI Express endpoint blocks), unless there will be identical custom functionality created in the ASIC.

Question: What advice do you give to your customers when integrating their FPGA device to the PCB with respect to SSO/SSN? Decoupling? Routability? Escape area and escape planning with respect to signal layers? Thermal Issues?

Answer: Refer to the following whitepaper on Xilinx.com “Methodologies for Efficient FPGA Integration into PCBs”: www.xilinx.com/bvdocs/whitepapers/wp174.pdf.

Question: Do you provide specific advice for dealing with differential signals? If yes, what is it?

Answer: Refer to the “Transmitting DDR Data Between LVDS and RocketIO CML Devices” application note on Xilinx.com: www.xilinx.com/bvdocs/appnotes/xapp756.pdf.

Question: How do you recommend global and local/regional clocking be handled?

Answer: Xilinx’s latest Virtex-5 devices contain Complete Clock Management to address complex timing requirements: www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/clocking.htm.

Question: What issues are you seeing with combining IP blocks? What advice can you give for engineers shopping for IP?

Answer: There are a few minor challenges in combining IP blocks, primarily due to subtle differences in what is delivered by the IP vendor and the format of those deliverables. A bigger challenge in combining IP blocks is ensuring that the customer design can still meet the timing requirements and resource requirements. The most important piece of advice for engineers shopping for IP would be to confirm how the IP vendor has verified and validated the IP, i.e., confirm quality and ease-of-use.

Question: Do you have any recommendations for FPGA engineers working with other members of their team, like the layout engineer, systems engineer, and so on? What team approach should be applied to complex and/or high-speed FPGA designs?

Answer: Xilinx offers the PlanAhead Design and Analysis Tool. It provides hierarchical, block-based, modular, and incremental design methodologies, enabling members of a design team to change only part of the design. This leaves placement of the rest intact, thereby shortening design iterations and minimizing impact of multiple designers. It helps design teams consistently maintain the required performance, even while making frequent changes. PlanAhead also facilitates IP reuse.

Question: How do you help your customers get from concept to manufacturing?

Answer: Much of the focus with Xilinx Design Tools has been to address what’s being communicated as the number-one challenge for FPGA designs—achieving timing closure. With ISE 9.1i, Xilinx introduced SmartCompile Technology to help users reduce the verification, implementation, debug, and system-integration steps within their design. In general, it’s easier and faster to preserve a design than it is to re-implement it. Therefore, if most of the design can be preserved using SmartCompile, the time to implement the design will be shorter. The average runtime improvement seen in an extensive design suite used to test these techniques is about 2.5 times faster than the initial implementation. That is, if a design takes three hours to implement, the subsequent implementation using design preservation is a little over an hour. In some of the best-case scenarios, the run-time improvement is up to six times better than the initial implementation.

Another advantage of design preservation is reduced verification. If a block of the design is exactly preserved, then that portion of the design needn’t be reverified after a design modification. Because the preserved implementation is exactly the same as the previous implementation, the placement, routing, and timing will be the same. Therefore, re-verification isn’t necessary.

Question: Are you working with EDA companies to better define up-front constraints that ideally could be applied and live with the FPGA throughout the design process?

Answer: Xilinx is continually working with EDA partners to improve the FPGA design environment for users. One example is the Ultra-High Density Task Force announced in May 2006. One of the most obvious results from this partnership was the SmartCompile introduced in ISE 9.1i. Through joint development between Xilinx and Synplicity, users have access to an environment by which the synthesis products from Synplicity can confine the change to a limited area of the overall design. Then, what gets propagated to the Xilinx back end is the information specific to the pieces of the design changes. Based on the previous implementation of the design, ISE 9.1i has more information on how to handle only the portion of the design affected by the change.

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