Electronic Design

Generate Those Low Voltages Needed For FPGA-Based Boards

It's now common for FPGA-based boards to require as many as four or five different low-voltage supplies to power the various components.

It's now common for FPGA-based boards to require as many as four or five different low-voltage supplies to power the various components.

First it was 3.3 V, then 2.5 V, 1.8 V, 1.5 V, and now 1.2 V. Each new FPGA generation seems to require a new low supply voltage.

On top of that, new communications and memory technologies (such as DDR Memory and DDR-2) require additional new I/O supply voltages and termination voltages. Now, FPGA-based boards frequently demand four or five different low voltages to power the various components.

At the same time, increased CMOS gate counts and higher clock speeds have resulted in higher power requirements. For example, Altera offers 14 different products in its Stratix/Stratix GX family of FPGAs. In terms of power required, the smallest FPGA clocking under 100 MHz will need less than 1.5 W of peak power for the core logic, whereas the largest version will need almost 21 W for the core logic when clocked at 300 MHz.1

These trends are forcing board designers to use more and higher-performance power supplies. Fortunately, the latest generation of low-voltage power-management ICs is keeping pace with the challenges presented by these high-performance boards.2

LATEST-GENERATION FPGA POWER REQUIREMENTS
A large part of the value of FPGAs is their flexibility. For example, the Stratix/Stratix GX family mentioned above ranges in functionality from 10,570 logic elements (LEs) to over 79,000 LEs.3 The number of LEs and other internal blocks used simultaneously determines the peak gate usage. Along with the switching frequency and operating voltage, this sets the peak power consumption, which depends heavily on the total system requirements. All major FPGA vendors have online "power estimators" that let customers describe their designs in terms of blocks used and switching frequency and use these inputs to calculate the expected power-supply current and power consumed.

FPGA-based board designers face the uncertainty about the system's actual power requirements because the gate-level design typically isn't finalized before the hardware is first generated. (The flexibility of FPGAs allows this, so engineers should take advantage of it!) Another major issue for power-supply designers involves dynamic load requirements, or transient performance. The FPGA load may quickly go from an inactive, low-current state to a fully processing state or vice versa, and accurate regulation needs to be maintained. Transient conditions like this one typically aren't a part of the company's power calculators, so the board designer must make estimates of worst-case transients and design the power-supply circuit accordingly.

Core Logic Power:
In large FPGAs, the logic core generally has the most demanding current requirements—up to tens of amperes, depending on the number of gates being used and the clock frequency. On the positive side, once the FPGA family is selected, the core logic supply voltage is set (as shown in the table, for example). This core logic supply is designated VCCINT by both Xilinx and Altera.

Maximum current estimates can be found in FPGA power application guides or calculated using the online power estimators. These maximum current estimates let the hardware engineer design a power supply that will be sufficient for the design, even if the block usage and design in the FPGA hasn't been finalized.

I/O Power:
In the latest generation of FPGAs, over 15 different I/O standards are offered with various required voltage levels. However, usually 1.5, 1.8, 2.5, or 3.3 V is required, depending on the I/O standard. Because I/O standards can be set independently by the I/O block in the FPGA, more than one I/O voltage for a single FPGA is possible. I/O current requirements depend on the number of I/Os used and the clocking speed.

Generally, even in the largest FPGAs, I/O currents are less than 3 A (which, given the generally higher voltage than the core logic, may still be up to 10 W of power). Because the I/O voltages required by an FPGA are determined by the devices that interface with the FPGA, often the supply generated for the FPGA's I/O can be shared to power the I/O of the companion device and possibly other circuits.

VAUX Power: The "auxiliary" supply is important for the latest generation of Xilinx FPGAs because it's tied into the JTAG, DCM, and other circuitry. It's designated VCCAUX and is usually 2.5 or 3.3 V. VCCAUX must be sufficiently decoupled to avoid power-supply transients coupling into the FPGA's clock.

Due to these power requirements, the supply must generate at least one and often two or three voltages below 3.3 V. Typically, this means using a switching buck regulator or a linear regulator from a higher voltage bus (+3.3, +5, or +12 V are currently the most commonly available) down to the required low voltage.

But linear regulators are inherently inefficient because they drop the voltage across a variable resistor (the pass transistor). Therefore, the load current times the voltage drop equals the power dissipated in the device. At the current levels required by the newest generations of FPGAs, this also can generate large amounts of heat. In battery-powered systems, efficiency is typically the driving requirement for using a switching regulator instead of a linear regulator. In wall-powered systems, heat considerations usually move designers to use switchers instead of linears.

For example, assume a fully used Xilinx Virtex-II XC2V250 clocking at 100 MHz, or an Altera Cyclone EP1C20 clocking at 175 MHz, powered from a 5-V input. The power required is:

VCCINT = 1.5 V 
ICCINT = 1.1 A (approximately) 

For a linear regulator:

PowerLinear = IOUT X (VIN − VOUT) = 1.1 A X (5 V − 1.5 V) = 3.85 W

Temperature of T0-263 package (LM317S) = 217°C (50°C/W; assumes 0.5 in.2 copper area)

For a switching dc-dc regulator (EL7562 2-A regulator):

Efficiency = 87%; power loss = 0.22 W; temperature of package = 40°C (0.5 in.2 pc-board area required)

Pulse-width-modulation (PWM) switching regulators are inherently more efficient because they transfer current through low-resistance power MOSFETs. Also, the voltage is "dropped" on the inductor. Switchers can maintain PowerOUT/PowerIN efficiencies in excess of 90%, even with very different input and output voltages and current requirements ranging from milliamps up to 100 A. The type of regulator should be determined by efficiency requirements, thermal-management strategies, space constraints, and cost. In many cases, there's a good reason to use both types of regulators in a design.

A PRACTICAL EXAMPLE CIRCUIT
Figure 1 shows a single-IC solution for generating four supply voltages from one +5-V input. A more detailed schematic is available at www.intersil.com/Xilinx or www.intersil.com/Altera. The ISL6521 synchronous buck regulator includes three linear regulator/controllers, which can provide additional voltages to the board. I/O and IAUX currents under 120 mA can be supplied directly from the linear-regulator output pins (as shown for 2.5 and 1.8 V). Or, they can be used to control an external transistor (as shown here for 3.3 V). All output voltages are fully adjustable with resistor dividers.

The ISL6521 automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the input bias supply voltage at the VCC pin, and the POR function initiates soft-start operation after the bias supply voltage exceeds its POR threshold. All voltages rise monotonically and in less than 40 ms, which is often a requirement for FPGAs.

Current IC and module technology can attain very high levels of isolation between each output on a single IC or in a single package. The cause of board-level supply coupling is more likely to be poor external component selection and layout mistakes, rather than having two supplies share one IC.

For this example, it's assumed that a +5-V power rail is available and the FPGA selected requires a core voltage of 1.2 V at 2 A. Selecting switching components to support the FPGA core starts with a few basic buck converter principles. First, the duty cycle required to produce the desired output voltage is checked against the maximum of the switching regulator IC. Duty cycle (d) is defined for a buck converter as:

d = VOUT/VIN (1)

For this design example, the resulting duty cycle is 24%. The ISL6521 supports operation from 0% to 100% duty cycle, but the output-voltage range is limited to between 0.8 and 4.5 V. Not all controllers support the entire duty-cycle range. This could pose a problem when dealing with load transients at extreme ends of the output-voltage range.

The FPGA core-voltage accuracy requirements vary by series and vendor. An FPGA core voltage with a required accuracy of +5%, or 60 mV, is typical and assumed for this example. This must be compared to the output-voltage regulation of the controller, which is 2%, or 24 mV. If the output-voltage regulation of the controller IC is greater than the FPGA's core-voltage required accuracy, the controller in question won't meet the FPGA requirements.

The difference between the FPGA's required accuracy and the output-voltage regulation of the PWM leaves the output-voltage window to support the switching power supply's output-voltage ripple and allowable transient deviation. The available output-voltage window is calculated:

Voltage window = (required accuracy − output-voltage regulation) X VOUT (2)

For this example, the voltage window is 36 mV. The peak-to-peak output-voltage ripple is selected next, and a reasonable value of 10 mV is chosen. The output-voltage ripple must fall within the voltage window calculated or a controller with a tighter regulation tolerance is required. Selecting larger output inductors or lower equivalent-series-resistance (ESR) output capacitors can reduce output-voltage ripple.

Once the output-voltage ripple is set, the transient-output-voltage window sets the minimum ESR requirement for the output capacitor(s). The transient window is centered around the FPGA core voltage, 1.2 V, and limits the transient excursion of the output voltage in each direction. The output voltage drops in response to a positive step in output current. This drop must not exceed the transient-output-voltage window. Therefore, assuming the slew rate of the transient is negligible, the target output capacitor ESR calculation (ESRMAX) is:

ESRMAX = (voltage window − \[ripple/2\])/(ISTEP) (3)

where ISTEP is the maximum step change in output current by the load. The reverse is true when the load drops off at the same step magnitude.

The FPGA power calculator can be run for the before-and-after-transition states to calculate the expected current change. Remember that both positive and negative power changes must be considered to make sure the design maintains the required voltage regulation for the FPGA. For a simple, worst-case analysis, a load step equal to the maximum output current can be used. The resulting target output capacitor ESR is 15.5 mΩ for this 2-A step design. Before an output capacitor is selected, the minimum inductance required for the design must be calculated:

LMIN = \[ESR X VOUT X (1 − d)\] / (Fsw X ripple) (4)

The switching frequency (Fsw) of the ISL6521 is 300 kHz. The resulting minimum inductance for this design is 4.56 µH. Inductors typically have a 10% to 20% tolerance and should be sized larger than the minimum calculated to support this tolerance. The inductor selected, LOUT, for this design is a Toko D104C series part with the following specifications: 6.4 µH, 5.2 A, 22.9 mΩ DCR, SMD.

Finally, the minimum output capacitance required for the design is calculated. The ESRMAX value calculated previously and the minimum output capacitance value dictate the type and minimum number of output capacitors needed to meet the voltage-tolerance specifications and transient response. The minimum output capacitance for this design is 324 µF:

COUT MIN = \[LOUT X (current step)2\]/\[(voltage window − ripple + VOUT)2 − VOUT2\] (5)

Based on these requirements, one Panasonic EEFUE0D391R (12 mÙ, 390 µF) specialty polymer aluminum electrolytic chip capacitor supports these requirements. Refer to the ISL6521 datasheet for instructions on the PWM controller compensation.

The final piece of the component-selection puzzle is power MOSFET selection. Power dissipation and package selection drive this process. Conduction loss and switching loss compose power dissipation. These losses are distributed between the upper and lower MOSFETs, according to the duty cycle.

The conduction losses make up the main component of power dissipation for the lower MOSFET. Only the upper MOSFET has significant switching losses, because the lower device turns on and off into near zero voltage. The ISL6521 datasheet supplies equations to calculate these losses. Other selection criteria include package size, which affects both board area and height off the board. Typically, an eight-lead SOIC package will support the power, cost, and space limitations in 10-A or lower designs.

Power-device selection for the linear portions of the controller IC is driven mainly by RDS(ON), current gain, and thermal considerations. The internal drivers can provide up to 120 mA of load current without an external pass device. Based on this current drive capability, external bipolar npn transistors can support loads of up to 3 A. The main criterion for choosing transistors is package selection for efficient heat removal. The power dissipated in a linear regulator is:

PowerLinear = IOUT X (VIN − VOUT) (6)

Select a package that maintains the junction temperature below the package rating with a maximum expected ambient temperature. The current gain at a given operating VCE must be sufficiently large to provide the desired maximum output load current when the base is fed with the minimum driver output current of 100 mA.

LAYOUT RECOMMENDATIONS
Layout is a crucial factor in on-board switching-power-supply design. With power devices switching efficiently at greater than 200 kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress.

Careful component layout and pc-board design help suppress the voltage spikes in the converters. As an example, consider the turn-off transition of the upper PWM MOSFET. Prior to turn-off, the MOSFET carries the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short but wide traces minimize the magnitude of voltage spikes.

A switching dc-dc converter has two sets of critical components. The switching components (power FETs and inductors) are the most critical because they switch large amounts of energy, and therefore they tend to generate large amounts of noise. Next are the small-signal components that connect to sensitive nodes or supply critical bypass current and signal coupling.

Place the switching components close to the device first. Minimize the length of the connections between the input capacitor(s), CIN, and the output power switches (whether external with the ISL6521 or internal in the EL75xx family) by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible.

The critical small-signal components include any bypass capacitors, feedback components, and compensation components. The feedback resistors should be located as close as possible to the relevant FB pin, with vias tied straight to the ground plane as needed.

Finally, a multilayer pc board is recommended. Dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Make sure that the metal runs are short from the PHASE or LX terminals to the output inductor.

The wiring traces from the GATE pins on the ISL6521 to the MOSFET gates also should be kept short, and they should be wide enough to easily handle the 1 A of drive current. The power plane should support the input- and output-power nodes. Use copper-filled polygons on the top and bottom circuit layers for the phase nodes. For small signal wiring, use the remaining printed circuit.

A SMALLER SOLUTION
The technology for high-performance switching dc-dc power supplies has progressed dramatically in the past few years. It's now possible to purchase devices that require only a few external components (usually an inductor, a few capacitors, and a few resistors) to generate a well-regulated, highly efficient supply voltage. Often, these ICs also include features such as overvoltage protection, supply sequencing capabilities, and soft-start.

One example is the EL75xx switching dc-dc power supply family, which can supply between 0.6 and 8 A of output current. The EL75xx family can convert down from VIN = 3.0 to 6 V, to as low as 0.8 V for VOUT. This covers all major FPGA-core and I/O voltage levels. The design shown in Figure 2 can implement up to a 25-W supply in less than 0.72 in.2

A 1-A output supply (approximately 4 W max) can be created from another member of the family, the EL7531, in 0.18 in.2 This family of ICs achieves efficiencies as high as 95%. Some, including the EL7531, have a pulse-frequency-modulation (PFM) mode that can be used for "light" loads to keep efficiency above 75% even down to low output-current levels (e.g., 10 mA) under most conditions.

COMPONENT SELECTION
By integrating the power FETs and the compensation/feedback circuitry, power supplies built with products like the EL753x simplify the design task and minimize the required board area. In exchange, the customer has less flexibility to tailor the feedback compensation to optimize performance for a given system.

Output Inductor: Because of the EL753x's internal compensation, the range of allowable inductors is relatively narrow. For the EL753x family, an inductor value of 1.5 to 4.7 µH is recommended. This small inductor value is critical to minimizing the total board space of the power supply and is a direct result of the high-frequency switching inside the EL753x. Selecting the output inductor is also heavily influenced by the required transient response of the supply, as discussed in the ISL6521 equations above.

I/O Capacitors: The EL753x requires a minimum 4.7 µF to ensure proper and stable operation during extreme load and temperature conditions; the recommended I/O capacitance is 10 µF. Selecting the type of capacitor is especially important to maintain the required performance over temperature. For example, a Y5V capacitor loses its ability to store charge by up to 50% at −40°C and 85°C, while an X5R's and an X7R's capacitance is a weaker function of temperature. These types of dielectrics are the best candidates for most applications.

References:

  1. Source: Altera Stratix Power Calculator online.
  2. Refer to www.intersil.com/data/AG for Applications Guide for Powering Xilinx FPGAs and DDR Memory, Applications Guide for Powering Altera FPGAs and DDR Memory, and Applications Guide for Powering Actel FPGAs and DDR Memory.
  3. Source: www.altera.com/products/devices.
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