Electronic Design

Get Unlimited In-System Reconfiguration With Analog Front End

Earlier members of Lattice Semiconductor's ispPAC programmable analog family were modest in terms of performance, integration, and field reconfigurability. But the latest addition brings a new level of complexity and dynamic reconfigurability.

Along with higher integration and improved bandwidth of operation, the ispPAC30 delivers greater flexibility via dynamic in-system configuration of gain, analog routing, precision voltage reference, output amplifier configuration, I/O, and other similar features. Plus, it incorporates on-chip SRAM and EEPROM memory for unlimited reconfiguration.

As a result, users can program the chip in EEPROM as a starting configuration and then reconfigure the device during system operation using SRAM cells, says Andy Robin, vice president of new business for Lattice Semiconductor. While the SPI and SRAM combination enables real-time in-system adjustments, the SRAMs permit un-limited reconfiguration of the device, he adds.

Key on-board functions include four instrumentation amplifiers, two precision references with programmable output voltage, two true four-quadrant multiplying digital-to-analog converters (DACs), two output amplifiers, an enhanced analog routing pool, a JTAG/SPI interface, offset auto-calibration, 2.5-V reference, and memory.

In short, it provides all the typical signal conditioning functions for a data acquisition circuit and 8- to 12-bit analog-to-digital converters (ADCs). Maximum frequency of operation is 1.5 MHz. Other features include differential and single-ended inputs, single-ended rail-to-rail output swing, 10-µA standby current, and single 5-V operation.

Version 1.3 of the PAC-Designer software is an intuitive schematic design entry and simulation tool with support for ispPAC30. The manufacturing-support library functions, a new capability introduced in PAC-Designer v1.3, can be used to automatically calibrate the analog parameters of the circuit in the manufacturing line to compensate for other components' tolerances. This version can be downloaded from Lattice's Web site.

Implemented in 1.0-µm CMOS, the ispPAC30 comes in 24-pin SOIC and 28-pin DIP packages. In 1000-piece quantities, it costs under $7.00.

Lattice Semiconductor, 5555 N.E. Moore Court, Hillsboro, OR 97124; (503) 268-8000; www.latticesemi.com.

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