The importance of hardware-based acceleration is growing for specialized computing applications whose performance requirements exceed the capabilities of general-purpose CPUs. Couching algorithms in silicon can deliver orders-of-magnitude improvements in speed for cryptography, real-time video, 3D imaging, IP telephony, and other science, engineering, and business applications.
The accelerator market is specialized. A kaleidoscope of vendors has developed solutions tailored to specific industries, processors, operating systems, and other variables. These solutions are created as needs arise, with no overall plan or strategy behind them.
There are multiple form factors for accelerators, multiple ways of physically connecting them to systems, and multiple ways for them to communicate with the motherboard. All of this chaos means that choosing which acceleration technologies to use and figuring out how to get the most out of them are daunting propositions.
This challenge contrasts with the rest of the computing industry, where increasing openness provides more choice and flexibility for users. The same should be true of accelerators. Ultimately, users who can benefit from hardware acceleration should be able to choose any accelerator on the market that suits a given purpose and plug it into a system as easily and seamlessly as if they were plugging in a mouse or a monitor. By making it easier for people to use accelerators, the accelerator industry can grow and bring greater benefits to businesses and research.
Industry standards are vital in easing the adoption of hardware acceleration. Today, accelerator developers typically provide customers with proprietary software that allows the accelerator to communicate with the computer system. This adds to the cost of developing accelerators and can limit the ability of users to migrate among technologies as their needs change. In the future, standardized protocols will replace accelerator-specific software interfaces, enabling customers to choose the hardware that is right for them and enabling vendors to focus on developing better accelerator technology.
Most accelerators connect to systems using PCI Express (PCIe) technology, an open industry-standard interconnect. In an example of the kind of industry cooperation that’s necessary, the PCI-SIG announced the next-generation PCI Express 3.0, which will address new and emerging application needs with innovative extensions. Wider use of PCIe as an interconnect for hardware acceleration will move the accelerator industry toward open and widely used standards, helping to remove barriers to adoption.
This is the idea behind Intel’s QuickAssist Technology Accelerator Abstraction Layer (AAL), which provides both a standard user interface for accelerator functions and a set of services for handling canonical functions like discovery and binding. Currently, AAL is used for FPGA accelerators coupled to the CPU via the Front Side Bus (FSB), but the idea could be extended to physical couplings of various kinds. Intel is working closely with vendors of FSB-coupled accelerators to get their input on AAL and provide them with everything they need to move to a more open interface model.
Many companies are experimenting with ways to lower the cost and complexity of hardware acceleration while increasing the number of applications for the technology. Strategic cooperation is in the best interest of everyone involved, as the computing industry as a whole is converging around solutions that provide flexibility along with enhanced performance.