More embedded projects are incorporating multiple processors. Recognizing this opportunity, MIPS (www.mips.com) has delivered the MIPS M4K multiprocessor core. This MIPS32-based core improves performance and eases development in multiprocessor environments.
The M4K core addresses a number of areas that are key to multiprocessor system design, such as improved interprocess communication, specialized debug support, and enhanced configurability. In addition, the M4K eliminates the usual data cache, using instead low-latency, on-board SRAM to speed data movement. Eradicating the cache also helps reduce the die size. The most compact version of the M4K is approximately 0.3 mm2. The 0.13-µm G process uses 0.1 mW/MHz and runs at 200- to 240-MHz speeds, while the 0.13-µm LV process consumes more power and operates in the 250- to 300-MHz range.
The architecture employs a five-stage pipeline. It includes MIPS32 enhancements and supports user-defined instruction-set extensions and compact MIPS16 instructions. New bit-field manipulation instructions have been added, and a new SYNC instruction forces memory access synchronization among multiple processors.
The chip handles up to four zero-overhead context switches in hardware. Vectored interrupts are also supported, as are 64-bit coprocessors.
Debug enhancements were key to improving multiprocessor debugging. Hardware-based multiprocessor breakpoints are possible with a new TAP interface. The ability to stop multiple processors when a particular instruction or event occurs is often necessary when tracking down difficult bugs.
The M4K makes significant strides in multiprocessor integration and debugging. It's a good choice for new multiprocessor designs.
