Electronic Design

Hardware Products

1-GHz Pentium III Drives VME SBC
(800) 322-3616, www.vmic.com

Pentium-class processors have built a large base in embedded servers, even in VME. Today, these servers run with the latest Pentium chips. VMIC's VME SBC builds on a 1-GHz Pentium III with 256 kB of advanced transfer cache and a 100-MHz external system bus.

Called the VMI/VME-7697, it supports the Intel processor with up to 128 kB of battery-backed SRAM and up to 512 MB of SDRAM, supplemented by up to 192 MB of nonvolatile, CompactFlash memory. This combination provides a fast local RAM, backed up by a slower, nonvolatile flash memory to hold key code and data. The flash memory can hold the program and data for dedicated applications, but it also enables developers to change the on-board program and data as needed. Special SBC features are a PMC mezzanine site for modular I/O expansion and a remote Ethernet boot-up capability. On-board peripherals include a programmable watchdog timer, a 64-bit AGP SVGA graphics controller with 4-MB SDRAM, a fast Ethernet controller, an Ultra-DMA-33 hard drive and floppy drive controllers, an SCSI-2 controller, 2 16550 serial ports, a parallel port, PS/2 keyboard and mouse controllers (front-panel ports), and a front-panel USB port. The SBC runs with Windows NT/2000, VxWorks, Solaris, QNX, LynxOS, Linux, and other major OSs. Prices start at $4473.

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PIC 8-Bitter Goes ROMless
Microchip Technology
(480) 786-7668; www.microchip.com

Over the years, microcontrollers have packed more and more memory on-chip, but sometimes off-chip memory has its advantages. For one thing, off-chip memory lets designers tailor memory size to the application and adjust the memory mix—RAM, ROM, and flash—as needed. The 25-MHz PIC18C60-1/801 8-bit microcontrollers are the first Microchip PICs as ROMless parts. They address up to 2 MB and 256 kB of off-chip memory. Both chips interface to 8- or 16-bit memory interfaces. Each provides 2-chip selects for memory addressing. On-chip, the processor gets 1536 B of RAM, including the processor registers. To move data between the on-chip and off-chip memory, the CPU provides Table Reads and Writes that move data between the spaces through an 8-bit register.

An 8-bit RISC-like architecture includes a 2-stage pipeline, an 8-bit datapath, and a 16-bit instruction word. Peripherals include an I2C and SPI serial ports, and an addressable UART. It also has a programmable low-voltage detector, a PLL for high-frequency oscillators, and a 12-channel 10-bit ADC. The chip features a PWM module and up to 47 digital I/Os, an 8-/16-bit timer-counter with an 8-bit prescalar, a 16-bit timer-counter, and an 8-bit timer-counter. The PIC18C801 and PIC-18C601 cost $4.06 and $3.40, respectively (10,000).

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SoC lntegrates ARM RISC, USB, Bluetooth, Audio
LinkUp Systems
(408) 988-3848; www.linkupsys.com

New applications like Smartphones, PDAs, wireless portables, and Internet appliances are driving ASSPs. These are tailored SoCs, integrating a processor with application-level peripherals for a high-integration design block. The latest SoC is LinkUp Systems' L7210, an ARM RISC IC with Bluetooth wireless, USB, serial audio, and Secure Card connectivity. It's the latest memory in LinkUp's L7200 family of ASSPs for low-end, low-power applications such as PocketPCs, Smartphones, feature phones, wireless Internet terminals, WEBpads, and other portable applications. It integrates a 50-MHz ARM720T RISC CPU (8-kB unified cache), 80 kB of SRAM, and a 1-kB boot ROM.

An on-chip SVGA graphics controller supports 640- by 480-pixel STN, DSTN, and TFT LCDs, a PC Card/CompactFlash controller and interface, a Secure Digital card interface, an AC-97 serial audio interface (stereo audio codes and modem codec), 3 UARTs with DMA (to 920 kb), a UCB 1200 serial interface, an audio interface (MPEG audio decoding), an SPI/Microwire serial port, 2 16-bit counter-timers, 72 digital I/Os, and a 32-bit RTC. It also includes a USB 1.1 host controller with 2 ports. For low power, the CPU has power management with 5 states including snooze, standby, and deep sleep. It implements the ARM Thumb subset to execute a 16-bit ISA subset that minimizes bus-code accesses and code memory. The L7210 costs $25 (10,000).

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8052 + Transceivers = Internet Appliance
(418) 681-8022; www.domosys.com

Embedded systems are shifting to embedded-linked processing. More and more commercial, industrial, and consumer devices are hooking up to the Internet. One way is to combine an embedded microcontroller with transceivers to connect on its own. Domosys does that with its U-Chip, an 8052 that has transceivers to link up with narrow-band spread-spectrum carriers. Aimed at low to mid-range processing, it integrates an 8052 core with 2 kB of RAM, 64 kB of flash, and 4 kB of boot ROM. Peripherals include a full-duplex UART, an SPI serial port (master or slave), a watchdog timer, and a carrier front end—a matched comparator, a modulator (2 PWMs), a demodulator, a 2-kB communications RAM to buffer messages, and an on-chip power supply. Glue logic connects the processor to its carrier front end.

The U-Chip supports many network protocols like PowerBus (from Domosys) and CEBus. It's packaged in a 28-pin SoC or 80-pin TQFP for 2.5- and 3.3-V operation in a −40° to 85°C industrial range. Pricing starts at $8.50 (10,000).

64-Bit MIPS RISC Runs At 1600 MIPS/W
NEC Electronics
(800) 366-9782; www.necel.com

Many embedded applications, like dataflow and networking, have turned to 64-bit RISCs for wide data-word processing. A leader here is the MIPS 64 architecture, which delivers compact RISC silicon with full 64-bit datapath processing. The latest such device from NEC is a 64-bit 200-MHz RISC for network appliances and portable applications.

It builds on the MIPS 64 ISA coupled with an implementation that melds dual-instruction-issue performance with low-power dissipation, delivering 400 peak MIPS (360 Dhrystone MIPS) at 250 mW. The superscalar CPU issues up to 2 instructions per cycle (1.4 average). It implements the MIPS III instruction set (no FPU, LL, LLD, SC, SCD instructions).

Designed for low power, the VrC4131's 4 power-saving modes include a new eXsuspend mode that turns off the PLL to cut dissipation. It also supports the MIPS 16 ISA, the 16-bit instruction-word extension that enables execution of compact 16-bit code, minimizing code fetches, and size.

On-chip support includes 2 16-kB I and D caches, a 100-MHz SDRAM controller, a real-time clock, and a PCI controller. Such PCI interfaces are relatively new, giving the processor an edge in easily interfacing to PCI peripherals.

A VrC4173 companion chip adds peripheral power to the CPU. It has a USB host controller (2 ports), a PC Card controller (2 channels), a PS/2 interface (2 channels), an AC-97 audio interface, keyboard/touch-panel controls, ADCs and DACs, and 21 general digital I/Os. The Vr4131 is sampling and costs $25 (10,000). The VrC4173 costs $20 (10,000).

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Superscalar G4 PowerPC Hits 733 MHz
Motorola Inc.
(512) 933-7753; www.motorola.com

The PowerPC has become a mainstream 21st century standard architecture composed of ICs, ASSPs, and ASIC cores. Motorola's G4 PowerPC, with its 128-bit AltiVec vector processor, is a major contender for large-scale multiprocessing, competing against high-end DSPs. It delivers a PowerPC ISA with powerful math processing. The latest MPC7450 G4 kicks CPU clock rates up to 733 MHz. It features a redesigned CPU that's optimized for superscalar operation.

With a new 7-stage pipeline, the G4's CPU issues up to 4 instructions per cycle (1 must be a branch). The execution units include 4 integer units (3 simple + 1 complex), a double-precision FPU, 4 AltiVec computation units (simple, complex, floating-point, and permute), a load/store unit, and a branch-processing unit. On-chip are 2 32-kB I and D caches (physically addressed, locking, and 8-way set-associative) and a 256-kB L2 cache. The 256-bit wide L2 cache promotes higher performance, providing more on-chip memory as well as a buffering mechanism for L1 caches. The chip supports an off-chip, 64-bit wide L3 cache for additional I and D buffering. An on-chip L3 cache controller has tags for 2 MB of off-chip L3 cache.

The G4 is now a mainstream processor for high-performance applications requiring large processor arrays. Mercury Computer and Sky Computer have shifted from DSPs to G4s. The key is the G4's AltiVec vector processor, which delivers SIMD processing across a 128-bit register set. In a single cycle (pipelined), it executes 16 8-bit, 8 16-bit, 4 32-bit, and 2 64-bit operations on addressed registers. One AltiVec instruction can expand into up to 16 executions on multiple fields in the addressed register. The vector engine also lets programmers interchange and map fields across registers in many combinations. The chip comes in 533-, 600-, and 733-MHz versions at $250, $295, and $370 (10,000).

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