Featuring the 2B1Q line code for two- or four-wire applications, the chipset is member of the 2B1Q HDSL (high-speed digital subscriber line) family of chipsets. It permits a single T1 or E1 board design to be populated with pin-compatible 2B1Q or CAP chipset solutions to meet a variety of worldwide service requirements. The chipset supports T1 operation per ANSI TR-28 and Bellcore TA-NWT-001210 and E1 operation per ETSI ETR-152. The two-chip solution is comprised of a digital signal processor and analog front-end VLSI. The DSP is based on firm's DSL-optimized billion operations per second software downloadable architecture. The architecture is well-suited for delivering a comprehensive suite of loop maintenance, diagnostics and fault isolation capabilities that are indispensable in service provider environments.