Electronic Design

High Efficiency Challenges Power-Management Design

Designers face the formidable task of providing high-efficiency power management for processors that operate at 1 V and below, at 100 A or more, and at gigahertz frequencies.

The semiconductor industry has always forced the power-supply industry to follow its trendsetting lead. For the last decade, that trend has been to cram more transistors into a single package, particularly microprocessors. This led to microprocessors with smaller feature sizes and tighter spacing between internal components. To be operational, smaller feature sizes forced the processors to operate at a lower voltage. This, in turn, required lowervoltage power supplies with greater design challenges than their predecessors of five to 10 years ago.

Designers can deliver low-voltage, high-current microprocessor supplies. But when you add the requirement for high efficiency (90% or better), the technology falls a bit short. It’s unlikely that the high-efficiency requirements can be met using present-day components and technologies, but it can reach about 70% to 80%.

To understand processor power-source requirements, check out the 2006 International Technology Roadmap for Semiconductors (ITRS). It projects operation at 1 V and currents in the 100-A region for processors in the year 2010. By 2020, the expected supply voltage will be 0.7 V at higher currents.

A voltage regulator-down (VRD) configuration with all of its components mounted directly on a computer’s motherboard now powers most processors. Most VRDs have an 8-bit voltage identification (VID) code whose eight input lines connect to the corresponding eight VID pins of the processor.

By sensing the microprocessor’s VID code, the voltage regulator sets the required operating voltage for the processor. The processor also can employ dynamic voltage identification that allows it to vary clock frequency and operating voltage “on the fly,” in response to the processor’s workload and the thermal environment.

Intel’s November 2006 Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines (www.intel.com/design/processor/applnots/313214.htm) is an example of present-day processor power management. These powersource design guidelines are for five different processors:

  • Maximum supply voltage: 1.4 V to 1.425 V
  • Maximum current: 75 A to 125 A
  • Tight output voltage regulation (±5%) under all line, load, and environmental conditions
  • Very low ripple, typically less than 10 mV rms p-p
  • Efficiency of 75% to 80%
  • Fast transient response, consistent with microprocessor clock frequency
  • Overvoltage protection
  • Overcurrent (short circuit) protection
  • Overtemperature protection
  • Thermal management of power-dissipating components
  • Relatively small package size so that the supply can be located close to its microprocessor load.

MULTIPHASE CONVERTER ICS
The only topology that can meet today’s processor power needs is the multiphase switch-mode converter. It employs two or more identical, interleaved cells connected so that their output is a summation of the outputs of all cells (Fig. 1).

To understand the advantages of the multiphase converter, look first at the shortcomings of singlephase converters relative to supplying high current and low voltage. With a conventional single-phase converter, the output ripple and dynamic response improve with increased operating frequency.

In addition, the physical size and value of the output inductor and capacitor shrink at higher frequencies. Unfortunately, after the frequency reaches a certain limit, the converter’s switching losses increase and its efficiency declines. This forces a design tradeoff between operating frequency and efficiency.

To overcome these single-phase frequency limitations, the multiphase cells operate at a common frequency, but are phase-shifted so that conversion switching occurs at regular intervals controlled by a common control chip. The control chip staggers the switching time of each converter; therefore, the phase angle between each converter switching is 360°/n, where n is the number of converter cells. Because cell outputs are in parallel, the effective output ripple frequency is n × f, where f is the operating frequency of each cell. This provides better dynamic performance and significantly less decoupling capacitance than a single-phase system.

Current sharing among the cells is necessary so that one cell does not “hog” too much current. Ideally, each multiphase cell should consume the same amount of current. To achieve equal current sharing, the output current for each cell must be monitored and controlled.

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Multiphase converters feature several important advantages. First, each cell delivers 1/n of the total output power, reducing the physical size and value of the inductors employed in each phase. Also, heat dissipation is distributed because power semiconductors in each phase only need to handle 1/n of the total power. This reduces any hotspot temperatures, increasing reliability and allowing higher total power capability.

Furthermore, equivalent frequency increases without incurring further switching losses, enabling the use of smaller equivalent inductances that shorten load transient duration. And, reduced ripple current in the output capacitor lowers the output ripple voltage and allows the use of smaller and less expensive output capacitors.

Multiphase converters also have some disadvantages that should be considered when choosing the number of phases. Primarily, there’s a need for more switches and output inductors below a certain power level than in a single-phase design, which leads to a higher system cost. Also, they require more complex control because of multiple converter cells. The possibility of uneven current sharing among the phases is possible. Finally, there’s added circuit layout complexity compared with a single-phase system.

As operating current requirements increase, there’s a need for more cell phases. An optimum design requires tradeoffs between the number of phases, current per phase, switching frequency, cost, size, and efficiency. Also, higher output current and lower voltage require tighter output-voltage regulation. Multiphase design decisions may employ any one of several available approaches.

One uses a pulse-width-modulation (PWM) controller IC with integrated MOSFET drivers. Yet heat and noise generated by the on-chip gate drivers affect controller performance. It’s impractical to cascade these types of chips to add more phases. Accurate current sharing is difficult with this configuration. And, three phases appear to be the limit. Another approach is to use separate controllers and separate gate drivers, with the PWM controller isolated from the heat and noise of the gate drivers. However, current sharing is more complex because the current-sense signal is routed to the controller. There are additional controller-to-driver delays because of the separated ICs as well.

Yet another approach is to use a controller with integrated gate drivers and built-in synchronization and current sharing. It would only permit an even number of phases, though. While it simplifies the design, it may result in unused or redundant silicon, pins, and external components. Most importantly, driver heat and noise generated on-chip can degrade controller performance.

So, existing topologies may not provide the freedom required in selecting the number of phases. The ideal solution is a scalable topology that makes it possible to easily add or remove any multiphase cell without sacrificing performance. This approach must be able to share current equally among the distributed phase cells. Such a technique minimizes parasitics and eases board layout.

CALL DRMOS FOR POWER EFFICIENCY
One approach for configuring a reduced-size, scalable multiphase converter is to apply Intel’s Driver-MOSFET (DrMOS) specification (www.intel.com/design/pentium4/papers/drmos.htm) of November 2004. Fairchild introduced its first version in 2006, and it follows similar parts from Renesas and NXP, formerly Philips (Fig. 2).

One key advantage of using a multichip module for a DrMOS device is that the individual MOSFET’s performance characteristics can be optimized, whereas monolithic MOSFETs produce higher on-resistance (RDS(ON)). However, the component cost of a multichip module may be higher than a monolithic equivalent. Nonetheless, the designer should view the cost from a system viewpoint. That is, space is saved, potential noise problems are minimized, and fewer components reduce production time and cost.

Fairchild’s FDMF8700 is part of a suite of highly integrated “FET Plus Driver Multi-chip Modules” for use in high-current synchronous buck applications supporting Intel’s DrMOS Vcore dc-dc converter standard. The FDMF8700 is a fully integrated powerstage solution offered in a space-saving 8- by 8-mm micro-lead frame (MLP) package.

By replacing a 12-V driver IC and three N-channel MOSFETs, the FDMF8700 saves 50% board space compared to discrete component solutions. The layout and size of the switches and driver die are optimized to enable higher-frequency operation.

Unlike discrete solutions whose parasitic elements combined with board layout significantly reduce system efficiency, the FDMF8700 module both thermally and electrically minimizes parasitic effects and improves overall system efficiency. In operation, the high-side MOSFET is optimized for fast switching while the low-side device is optimized for low RDS(ON). This arrangement ideally accommodates the low-dutycycle switching requirements needed to convert the 12-V bus to supply the processor core with 1.0 to 1.4 V at up to 30 A.

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The MLP 8x8 power package extends the concept of enhanced packaging. The integrated FDMF8700 module provides an additional efficiency gain of 1.5% to 2% for peak- and steadypower levels compared with discrete solutions using D-Pak packaging. The complete Fairchild family of DrMOS multichip modules includes the FDMF6700, FDMF8704, FDMF8704V, and FDMF8705 (Fig. 3).

Renesas Technology America’s R2J20602NP integrates a driver IC and high- and low-side power MOSFETs in a 56-pin quad flat no-lead (QFN) package that conforms to the integrated DrMOS package standard. This second-generation driver-MOSFET product operates at up to a 2-MHz switching frequency and has a maximum output current of 40 A. Operating at 1 MHz with VIN = 12 V and VOUT = 1.3 V, it achieves a maximum efficiency of approximately 89%. With an output current of 25 A, power loss is only 4.4 W.

The R2J20602NP complies with the European Union’s Restrictions on Hazardous Substances (RoHS) and with the DrMOS standard. Its high heat-radiation package offers a small (8 by 8 mm) mounting area. It also uses a wireless copper-plate construction technique for internal connections, reducing resistance and parasitic inductance within the package. Pins for largecurrent paths occupy most of the rear surface of the package and facilitate heat dissipation.

The NXP PIP212-12M also meets the DrMOS spec. It consists of a high side (control FET), a low side (synchronous FET), and a FET driver. The fully integrated device comes in a single surface-mount package with integral heatsink. It employs highperformance MOSFETs and a customized driver that monitors switching dead time and actively eliminates dead time without allowing the devices to go into cross conduction.

Its feature set includes functionality for sequencing. An onboard regulator provides 5 V in 12-V-only applications. Its built-in loss phase-detection circuitry suits multiphase applications. And, its VOUT sense allows current sense back to the PWM as well as multiphase current-sharing designs. With its integrated design, it can be used as the building block of buck regulators capable of greater than 30 A per phase and frequencies of up to 1 MHz per phase. Moreover, greater power densities are possible than with discrete solutions or previous integrated solutions.

MULTIPHASE PWM ICS
Semtech’s SC2447 is a high-frequency, dual-phase, PWM stepdown controller optimized for Philips and Renesas DrMOS. Both phases can source or sink load currents, suiting the SC2447 for networking system power. It uses fixed-frequency, continuousconduction peak current-mode control for good compensation and fast transient response.

The SC2447 generates two independent, 180° out-of-phase, 30-A outputs. Either inductor dc resistance or a precision sense resistor can be used for current-mode control. Inductor dc resistance sensing has the advantage of being lossless. Each phase has an individual closed-loop soft-start and overload shutdown timer.

Intersil’s ISL6307A controls microprocessor core voltage regulation by driving from two to six synchronous-rectified buck channels in parallel (Fig. 3, again). Microprocessor loads can generate load transients with extremely fast edge rates. The ISL6307A features a high-bandwidth control loop and ripple frequencies up to 12 MHz to provide optimal response to the transients.

The ISL6307A senses current by utilizing patented techniques to measure the voltage across the RDS(ON) of the lower MOSFETs or dc resistance (DCR) of the output inductor during the lower MOSFET conduction intervals. Current sensing provides the needed signals for precision droop, channel-current balancing, and overcurrent protection. A programmable internal temperature compensation function compensates for the temperature coefficient of the current-sense element.

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