Electronic Design

IC Packaging Gets Ready For The Big Squeeze

Advances continue in the packaging of ICs and IC subsystems as the demand for smaller, denser, and lower-cost electronics continues. The trend is toward 3D packaging using wafer-level techniques to take advantage of available packaging space in the Z direction. Designers also are using silicon through-silicon vias (TSVs) for greater packaging interconnect densities.

The semiconductor consortium Sematech and a number of other firms are promoting the TSV concept. “Three or four years from now, we will face significant new thermal and I/O density requirements that require greater investment in packaging,” explains Michael Cadigan, general manager for semiconductor solutions at IBM.

These challenges as well as a move toward fabless design models (where packaging, testing, and assembly are outsourced) are making it very costly for packaging and assembly houses to keep up with rising capital equipment costs. Nonetheless, packaging and assembly firms are bracing for the future with greater funding, consolidation with other firms, and joint ventures with semiconductor IC manufacturers.

Indicating things to come in wafer-level packaging, Infineon presents an embedded wafer-level ball-grid array concept called eWLB (Fig. 1). A conventional WLB approach eliminates the need for an interposer layer, required in flip-chip packages to connect the I/O signal leads on a chip to their respective I/O balls to be soldered to a pc board. But this method also limits the number of I/O pins possible since all contact balls must fit under the IC chip’s shadow.

The eWLB method, on the other hand, is independent of chip size. It also allows the chip size to be shrunk by about 30% compared to conventional lead-frame packages.

An Interconnect Challenge
TSVs for 3D packaging are a hot topic—and for a good reason. According to the 2006 International Technology Roadmap for Semiconductors (ITRS), interconnect schemes are the key for nextgeneration manufacturing and packaging challenges. Also, interconnect scaling will no longer satisfy performance requirements. TSVs appear to be a promising solution.

The EMC-3D consortium of semiconductor IC equipment, materials, and R&D companies formed to quickly develop a TSV technology that’s manufacturable and cost-effective for 3D chip stacking and the integration of microelectromechanical systems (MEMS). The consortium expects results this year for the production of memory, specialty, and logic ICs, in that order. Critical parameters include etching rates, via depths, uniform via profiles, sidewall roughness, and thermal management.

Companies like Surface Technology Systems (STS) also are working to advance TSV technology. STS recently unveiled dry reactive ion etching (DRIE) of 150-µm deep TSVs on 300-mm wafers with a profile of 89.5º at a uniformity of ±2.5% using its Pegasus equipment. The etching rate was about 12 µm/minute, and sidewall roughness was about 600 nm. Nexx Systems performed the copper plating. For 3D packages, STS says it can produce via arrays with depths of 10, 20, 30, 40, and 50 µm.

EDA Tools
Improvements have been sporadic in the availability of supporting EDA 3D packaging tools. Large EDA vendors have been reluctant to support a vast array of 3D packaging methodologies. None of these methodologies has achieved some standard of normality or standardization, and they all require specialized EDA support tools.

“All of our EDA tools have over the years evolved from 2D models,” says Happy Holden, senior pc-board technologist at Mentor Graphics. “This makes it very difficult for EDA vendors to invest in 3D packaging until one or more methodologies become more popular and become mainstream. We’re in the formative years of 3D packaging.”

John Isaac, marketing development manager for Mentor Graphics’ System Design Division, concurs. “Until there is a broad market for 3D packaging, much of which differs widely, EDA vendors cannot invest in 3D packaging,” he says.

Holden sees two main categories evolving: stacked die and stacked packages. Each of these categories has many variations. He also points out that many different methods are being employed to achieve 3D packaging, and nearly all of them involve placing components on a pc board.

Since pc boards are here to stay, designers must deal with them when approaching 3D packaging. Holden says that the OCCAM process from Verdant Electronics provides many advantages for 3D packaging since it treats packaging as a “components-first” issue, not as a “chips-first” issue.

According to Holden, designers must pay attention to embedding passive components in 3D packages. While ICs with active elements are well integrated on a semiconductor substrate, they still require passive components like resistors, capacitors, and inductors to operate.

Thin-film and other techniques for shrinking such components have been around for decades. But the design of embedded passive components must be considered early on in the design cycle, if such embedded components are possible, and the proper EDA tools must be used for optimal 3D packaging results.

Perennial Challenges
Cost-effective packaging and heat-management techniques for dense ICs have always been elusive. Cost is particularly troublesome when it comes to non-standard devices like MEMS ICs. When MEMS IC volumes are high enough, proprietary packaging and assembly processes can be worthwhile to offset large capital investments in equipment and materials.

However, most MEMS devices are produced and packaged in smaller volumes. As a result, many MEMS companies are actively investigating novel methods of costeffectively making MEMS devices using conventional packaging approaches where MEMS ICs are joined together with standard CMOS ICs using standard packages.

One of these efforts has borne fruit at VTI Technologies OY. In the company’s Chip-on-CMOS methodology, MEMS and ASICs are manufactured on separate wafers to allow full testing of both types of wafers before wafer-level integration takes place (Fig. 2).

Thinned ASICs are flip-chipped onto the CMOS wafer in known good locations. Redistribution and isolation layers are applied to the MEMS wafer. Solder points are provided for external connection before the ASICs are added. The MEMS and ASICs are then isolated using a passivation layer.

VTI is looking to stack multiple ASICs atop its MEMS wafers for producing 3D stacks of very complex circuitry. It hopes to stack multiple ASICs that are 20 µm thick atop MEMS wafers at a much lower cost than existing 3D packaging techniques.

As for better heat management and removal, we may need a whole new set of materials and layouts to do the job. Increasing chip densities and signal speeds are challenging designers to come up with packaging materials and methods that can manage and dissipate the larger volumes of heat that arise from ultradense tiny packages.

Carbon nanotubes (CNTs) look very promising due to their high thermal conductivity properties. This is particularly important for power-type devices like high-power amplifiers and FETs. Carbon nanotubes (CNTs) and other exotic materials may have a large role here due to their high thermal conductivity. CNTs are still in the lab, but recent successful demonstrations at many companies portend their use in the not too distant future.

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