A large gap separates low-end networking solutions like CAN (controller-area network) or I2C and Ethernet. The Ultiwire I/O bus from Ultimodule Inc. looks to fill that void by using a novel single-wire protocol.
Ultiwire is currently implemented in an FPGA. Ultimodule builds a number of namesake Ultimodules, each with an FPGA like the SCM 220 (Fig. 1). A fraction of the FPGA is used to implement the Ultiwire interface, leaving the remaining logic for custom or standard peripheral support. Given the availability of high-capacity FPGAs, it will be possible to incorporate Ultiwire with soft or hard processors in a single FPGA.
Ultimodules are designed to work in a master/slave architecture (Fig. 2). Normally, the master incorporates the main processor and memory along with a Ultiwire master node. The master node connects to a daisy chain of Ultiwire slave nodes. Each slave node, which communicates with the master, contains an FPGA that implements an upstream and downstream interface. Each FPGA must be active to pass information between nodes.
Typical Ultiwire node interfaces require about 200 logic slices and 250 flip-flops in a Xilinx FPGA. The typical CAN A/B core uses almost twice that, but it operates at a lower speed. The Ultiwire support usually uses 10% to 50% of the FPGA, based on the FPGA's capacity. Because this still leaves a significant amount of logic for non-Ultiwire support, an Ultimodule may consist of just an FPGA.
The Ultiwire protocol uses small 16-bit frames with an 8-bit payload, so there's considerable overhead. But it also translates into very low response time. The configuration lends itself to the type of industrial automation I/O control Ultiwire is designed to handle, too. Likewise, slave Ultimodules include 16-channel digital ports, eight-channel analog ports, and two-axis motion-control modules with a limited number of ports.
Communication is initiated when the master node sends a TX frame. This is passed down the chain until it reaches the intended node that responds with an RX frame. Command and type fields in the TX and RX frames control the node actions. Reading and writing data is usually a multiple frame exchange, with the data field containing address information in the initial TX frames. All frames have a cyclic-redundancy-check (CRC) field for error detection. The RX frame's interrupt bit notifies the master of a status change.
Overall, Ultiwire implements a simple but fast communications link. Typical on-board connection distances are 0.6 meters. It supports cable lengths up to 5 meters. Longer distances are possible using low-voltage differential signalling (LVDS) or optical connections.
Ultimodules can plug into a carrier board so developers can easily mix and match control and I/O modules. Ultiwire supports up to 127 slave nodes per link. Multiple links provide a way to increase the bandwidth to the master. Redundant, multiple master configurations are possible. Ultimodule boards cost from $50 to $225 in OEM quantities. The Starter Kit costs $695. Third-party Ultimodules will ultimately make Ultiwire a more interesting standard.