Every year at about this time, the electronic design automation (EDA) Industry takes stock of itself. With the Design Automation Conference (DAC) just around the corner it's easy to understand why. For many, the success or failure of their company rests solely on whether or not they can have their product ready for introduction at or around the June show. What's hot and what's not seems to be the prevailing focus of most designers, me included.
What exactly are the main trends you, as a designer, should be aware of these days? Furthermore, what new products should you have on your radar screen?
In today's fast-paced, dynamic electronics industry, getting products to market on time has become quite a daunting task. Competition is fierce and growing stronger by the minute. Many view the Internet as the next frontier for designers. This is because it offers the flexibility and access to communication channels that will be necessary for survival in the coming years.
Until now, most of the movement onto the Internet has come from printed-circuit board (pc-board) vendors. The wide array of available products range from design services and component information retrieval services, to actual products that allow design via the web. To their credit, many of these vendors have pioneered the pay-per-use and monthly fee-based business models. By lowering the cost of entry, they have swung open the doors to a whole new segment of potential tool users.
Despite the efforts underway on the pc-board side of the design industry, IC vendors are no slackers. Though slower to the starting gate, their announcements as of late have been nonetheless significant.
For proof of this, you need to look no further than Cadence Design Systems. The company announced both a strategic initiative to support Internet-based electronics design, and a partnership with Hewlett-Packard and Flextronics International, culminating in the formation of a company called SpinCircuit Inc.
The initiative, iCadence, is intended to promote Internet-enabled design through infrastructure and content. This infrastructure will be able to bridge the gap between the supply chain and the EDA industry. Supported by this infrastructure, the content will feature a variety of tools and services, as well as portals such as www.SPECCTRA.com and www.Pspice.com. Both of these engineering communities will offer a variety of resources comprising educational forums, chat groups, product news, press releases, newsletters, contests, and beta-site application forms. User success stories and application notes will be included, too, along with software downloads, updates, patches, and free evaluation copies.
SpinCircuit will leverage the Internet as a means of bringing the electronics supply-chain network to the design desktop. Through its gateway, www.spincircuit.com, OEMs and engineers will be able to access the information they need to make design decisions early in the design process. This information will be available through a taxonomy-based component browser. It will contain an online database of design information featuring approximately two million parts (Fig. 1). An additional 250,000 parts will be added to the database each month. The company is currently working to establish universal standards for schematic-capture symbols and component taxonomies.
Toolwire hopes to mark out its ground as an Internet-based application service provider (ASP). Through partnerships with companies like Sun Microsystems, Lucent Technologies, Synopsys, and Avnet, it delivers software design tools, hardware servers, and virtually unlimited access to high-performance computing resources. All of this is available to designers on a 24-hour basis, regardless of their location.
Partnering with Hewlett-Packard Co., Monterey Design Systems has staked its claim to the Internet. The company's e-services offering includes remote access to both software and hardware through secured, high-bandwidth Internet and intranet connections to worldwide data centers. The current web-based design tools include E-Sonar, a front-end physical prototyping tool, and E-Dolphin, a physical design solution. Each may be purchased from Monterey's portal site on a global access, design portal, or time-based design business model basis. The result is access to global design on a 24 hour, seven-day-a-week basis.
Another occurrence of Internet partnering comes from Electronics Workbench. By collaborating with PartMiner Inc., the company now offers pc-board and PLD designers the ability to search for, identify, source, and purchase more than 10 million electronic components over the Internet (Fig. 2). This capability is available to users of the Multisim schematic and simulation tool. Access is provided to the PartMiner CAPSXpert electronic component database.
Novas Software Inc.'s latest offering, nEwhere, is guaranteed by the company to improve your productivity. It's 100% free and will work with any application (Fig. 3). This product enables design teams to work together, using Internet and intranet connections. Designed to promote team communication between designers of ICs, system-on-a-chip (SoC) ICs, and electronic systems, it allows online sharing of information. In other words, designers can see what their team members are doing and collaborate online to solve problems or debug a design.
The host user simply initiates an nEwhere session by publishing a URL and a password. Remote users join the session by entering the URL in their browser. During the session, the host shares information with remote users. Control may be turned over to a remote user at any time during the session. Remote users also are free to move or change on-screen information in order to make a point or ask a question.
Participants communicate through a chat dialogue and mark up the screen using a transparency layer. Voice interaction between the participants is handled outside the system through standard telephone or Internet telephony applications.
Barcelona Design is yet another example of a company offering web-based design services. Its initial product, Picasso Op-Amp Optimizer, is the first in a series of web-based chip design technologies. Offered as a pay-per-use service to engineers, the tool is targeted at designers that need to design analog and mixed-signal circuits containing op-amp functions.
Accessed through a standard web browser, the technology works by automatically generating an optimized netlist from user-defined specifications. This is possible for more than 50 types of op amps that cover a wide range of performance parameters and foundry processes. The Picasso Op-Amp Optimizer then gives users real-time feedback on possible design improvements or information about which specifications might need to be relaxed to best meet the overall design objectives. The system's tradeoff feature also can sweep constraints for a given objective.
This service is available now through June 15 at a special introductory price of $500 per design. Visit the site at www.barcelonadesign.com.
If you're looking for more information on the Internet trend, try DAC Sessions 15 and 43. Session 15, a panel discussion titled "EDA Meets .Com: How E-services Will Change The EDA Business Model," addresses the whole dot-com phenomenon. It examines the technology and e-services infrastructure that offer the most promise for enabling chip designers with new design capabilities. Furthermore, it discusses new business models for EDA companies ,and answers such questions as: how e-services will transform EDA sales channels and customer needs, and if they will change how end users design and vendors deploy their services.
The Web And EDA Research Efforts
Maybe you're curious about how this whole Internet-based design concept will work. Session 43, "New Frameworks For The EDA Field" includes a panel discussion on "Web-based Frameworks To Enable CAD R&D." This panel highlights different perspectives on the way the web will be used in the future to enable research and development processes throughout the EDA industry.
With the Internet media blitz raging around you, you might think that the only important things happening these days have to do with the web. Trust me, nothing could be further from the truth. Recently, there's been a great deal of attraction to a variety of topics, from next-generation lithography tools and timing closure, to moving test into the design flow. While these are certainly important issues, in the grand scheme of electronics design, the hot topic lately seems to revolve around one area—embedded systems.
Everywhere you turn today, you find products masterfully blended with just the right amount of hardware and software content. The embedded nature of these devices serves to mask their true complexity and brings a level of functionality never before possible.
As design teams migrate to true systems-level design and design geometries continue to shrink, you have to wonder where it will all end. How much further can we push the limits of technology? To put it bluntly, how will designers continue to crank out more embedded products with increased functionality, if the product's life span is shorter than its design cycle?
These are tough questions to answer and unfortunately they aren't the only issues facing today's designers of embedded products. How, for instance, can one model and analyze an embedded device? Which architecture should you use? How should system-level scheduling and compilation be handled? These tasks are time-intensive and difficult at best. Yet, learning to deal with them properly can take you one step closer to a successful design project.
One of the solutions for dealing with embedded devices involves the use of intellectual property (IP). Standards are now in development to encourage its widespread proliferation. A host of vendors presently offer tools that make using IP a much more manageable process. Interestingly, some vendors even look to the Internet for a means of increasing the ease by which designers can locate, examine, and design with IP.
If you're looking for more information on IP, you might want to check out session 36: "IP Protection And Reuse," or you could just cruise the show floor to see the latest IP-related products. Simutech, for example, has some intriguing IP evaluation technology you won't want to miss. In the end, whether or not you factor in IP or the use of other design components such as analog SoC, what really seems amazing is that embedded products ever get made at all.
Traditionally, the hardware and software sides of the world have remained isolated from each other, crossing paths in a joint design space only when it came to back-end integration and verification. For obvious reasons, this approach was wrought with problems. Since both teams designed in isolation, neither was aware of or made concessions to accommodate the other's constraints. Back-end integration problems were common and numerous.
In recent years, progress has been made to bridge the gap between the two design styles. Tools and technology have been introduced, enabling both sides to work closer together, as well as much earlier in the design flow. A perfect example of this would be co-verification. Another excellent example would be co-design, although still lingering are questions pertaining to when it will actually become a reality. Two of the more promising efforts in this area come from Cadence Design Systems and Synopsys.
Integrating Virtual Components
The Cadence Cierto Virtual Component Co-design (VCC) environment enables designers to integrate virtual components representing both hardware and software. Designers then can explore complex hardware and software tradeoffs, analyze product performance, and evaluate product architecture early in the development cycle. Functional and architectural modeling takes place at a high level of abstraction.
This environment features productivity-enhancing technology, along with access to software-estimation techniques, advanced performance modeling and partitioning, and interface communication synthesis technologies. The Cierto VCC also links to the Affirma hardware/software verifier for a complete hardware/software co-development design flow.
Synopsys' CoCentric System Studio, one of the most recent entries into the co-design space, will be available for general release in June. It's the first in a family of planned products centered on concurrent development of complex hardware and software systems. System Studio gives designers a way to quickly create executable system specifications and efficiently implement them as hardware and software functions. This is done by using multiple domain-specific abstractions in a single C-based environment.
By using System Studio, dataflow and extended hierarchical control models can be nested arbitrarily at any level of hierarchy. Users are able to describe their systems directly in C/C++, or the SystemC language. They also can incorporate existing Verilog and VHDL blocks. Dataflow and control functions may be defined by employing a graphical user interface. Processor models can even be included in the system description.
Just thrown into the mix, Mentor Graphics and Arexsys joined forces to offer co-design-like capabilities. They effectively integrated Arexsys' ArchiMate architectural exploration tool with Mentor's Seamless CVE co-verification tool. Seamless CVE, thus, can take the output from ArchiMate and verify the software against the prototype hardware. As a result, designers of embedded systems are able to design and debug embedded systems prior to their implementation.
However the co-design and other associated embedded systems design issues get worked out, it's apparent that taking either a hardware-centric or software-centric view of the problem won't work. What's needed are specific tools and technology. They must possess the ability to walk the fine line between both worlds. At the same time, they must provide designers with the flexibility to optimize for either the hardware or software portion of the design.
If embedded-systems design is your area of interest, be advised of DAC's June 7 technical program. It will feature an entire day devoted to presentations on this topic. Issues range from dealing with timing closure and designing with embedded SoCs, to the future of design languages. A panel discussion on the growing importance of embedded-systems design and its effects on the EDA landscape also is planned. That panel will feature top executives from leading software and chip companies.
SoC Versus Platform-Based Design
How can you talk about embedded-systems design today without mentioning system-level design and SoC? Three years ago, SoC was the topic of conversation everywhere you turned. It was the hot, sexy, new technology, guaranteed to solve all design problems, and everyone was migrating to it. In hindsight, the concept turned out to have a number of drawbacks that made, for many, the migration path a difficult one to follow.
Increasingly, design complexity makes an SoC more costly to manufacture and design. Timing-closure issues, signal integrity, co-verification, and co-design are just a few of the other obstacles facing designers today.
Complicating the matter of SoC and system-level design is the lack of a true system-level language. Many suggestions have been brought to the table recently, but none has yet emerged as the true victor. When it does, co-design may finally be realized and the role of co-verification in the design flow may become less expansive. Chances are this decision won't be arrived at quickly.
Even so, the high cost of design re-spins, and the fact that SoC design has became so terribly difficult, has led to the emergence of alternate design options. These options are seen as viable means of shrinking design time, and therefore, time-to-market, while simultaneously lowering the associated risk.
One solution is the use of FPGAs/PLDs for early prototyping and in some cases even volume production. Capacity of such devices—in the neighborhood of 2 million gates and still growing—has increased to the point where this is now feasible. These high densities, coupled with new, inexpensive, high-quantity programmable devices, has firmly established FPGAs/PLDs as a viable ASIC alternative, and in some situations an alternative to the pc board.
The other option is platform-based design. This is a way of making SoC design easier by having many of the basic building blocks—processor, memory, and interfaces—already designed and verified. Specific procedures are then added to the mix, allowing for the incorporation of pieces in the design and customization. The main benefit of this approach is that it minimizes design and verification. Expect to see a number of announcements regarding this topic later in the year.
Until then, if you're interested in more information on the concept of platform-based design, visit tutorial 3, "System-Level Design With Embedded Platforms." This tutorial introduces the y-chart methodology for designing systems that use embedded platforms. It details the concept of a separation between architecture and functions or applications, followed by the mapping of applications onto the embedded platform architecture. It also highlights trends in embedded systems and gives a definition of platforms. The impact of platforms on embedded systems and the importance of separating computation and communication will be discussed as well.
Furthermore, you might want to listen in on the keynote speech by Theo Classen, executive president and chief technology officer of Philips Semiconductor. His speech "First-Time-Right Silicon But To The Right Specification" discusses the real design challenge of the day. In his opinion, that challenge involves making a first-time-right specification and, the associated chip that implements this specification, correctly. According to Mr. Classen, fine-tuning of the system specification can usually only be done if an initial silicon version of the system has become available. As such, he details how the combination of Silicon Systems Platforms and the VLSI Velocity Rapid Silicon Prototyping can offer a solution to this dilemma.
If that's still not enough to whet your appetite, direct your attention to Surviving the SoC Revolution: A Guide To Platform-Based Design, by Henry Chang, Larry Cooke, Merrill Hunt and Grant Martin of Cadence Design Systems, and Andrew McNelly and Lee Todd of Simutech (Kluwer Academic Publishers, Boston, Mass., Nov. 1999). This book discusses all of the basics surrounding the platform-based design approach and gives you the information you need to start implementing it in real designs.
Session 38, "SoC Test Methodologies And Defect Modeling," covers the general state of SoC design. The same is true for tutorial 5, "Design Technology For Building Wireless Systems-on-Chip." You might also plan to attend the keynote address from Hugo De Man, senior research fellow of IMEC and professor at Katholieke University. His talk on "System Design Challenges In The Post-PC Era," will address the art of designing a diversity of low-cost, energy efficient, programmable platforms that can be configured over the Internet and communicated to humans through non-keyboard interfaces. His discussion further outlines the challenges associated with future design technology and the skill requirement of tomorrow's system engineers.
New SoC Products
In addition, you might want to visit some vendors debuting their new SoC-related products. Verplex, for instance, will be showcasing its Tuxedo-LEC 2.0 equivalence-checker tool and its ability to get full-chip functional closure in large designs. The tool can complete RTL-to-netlist functional comparisons of entire multimillion-gate designs. Even designs containing wide multipliers, handcrafted memory, pipeline retiming, state encoding changes, complex finite state machines, incomplete logic, and custom transistor logic, as well as designs produced by physical design tools, can be compared.
A prime feature of Tuxedo-LEC version 2.0 is its hierarchical module comparison manager. It allows users to quickly navigate and differentiate between functional bugs and benign hierarchy changes due to timing optimization. Plus, users can specify general constraints, a feature that's helpful in minimizing false negatives when verifying designs that have incomplete or missing blocks of logic. The tool now supports both VHDL and Verilog, in addition to EDIF. It ports to the latest 64 bit HP and Sun operating systems.
Mentor Graphics is making its splash into the formal-verification arena with the introduction of its FormalPro equivalence checker. Designed to overcome the challenges of verifying complex, multimillion-gate SoC designs, the tool has a capacity of 10 to 15 million gates and processes million-gate designs in a matter of minutes. This can be accomplished without partitioning the SoC or ASIC design into blocks.
Once the design has been read in, the tool performs matching, solving, and debugging. Advanced debugging technology carrys out automated analysis of failing comparison points and isolates the exact location of any errors.
FormalPro is built on an algorithmic-based approach, capable of reading VHDL and Verilog designs at the RTL and gate level, to prove functional equivalence between two designs. Multiple matching techniques and solver technology ensure an automated flow requiring little to no user intervention.
The Bottom Line
Whether or not the Internet, embedded systems, or SoC designs are areas of interest to you at this moment, chances are high that they will be in the near future. Keep yourself updated on these trends and you'll be off to a better start than most. If a problem hits, at least you'll know where to turn for assistance.
Until then, check the DAC program for more information on exact times and locations of the events mentioned in this article. You can retrieve that information from the site www.dac.com. Better yet, attend the show and witness the panel presentations, booths, and demonstrations yourself. The show will be held in Los Angeles, Calif., June 5-9, at the Los Angeles Convention Center.
|Manufacturers Of Products Mentioned In This Report|
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Novas Software Inc.