Electronic Design

Low-Speed Serial I/O Thrives Amid High-Speed Hype

Neglected amid the volume of recent press on high-speed serial interfaces, where the cutting edge is now exceeding 10 Gbits/s, has been the quiet adoption of lower-speed serial interfaces in a variety of equipment types. So why all the noise about high-speed interfaces, and what is driving the adoption of lower-speed interfaces?

Designers of cutting-edge networking and telecommunications systems often are limited by the amount of data they can transfer across their backplane. For a given physical size, board manufacturing technology, and number of layers, there is a finite and literal limit to the number of signals that can be placed on the backplane. This limit is squeezed further by the need to maintain separations and insert ground planes and traces to minimize crosstalk.

Such challenges prompted the switch from parallel buses running at lower speeds to higher-speed serial interfaces. Over time, designers have moved from 1 Gbit/s to 3 Gbits/s, and investigation in the areas of 5 Gbits/s, 10 Gbits/s, and higher is active. Due to both the inherent interest associated with the cutting edge and the improvements in the capacity of high-end systems that the latest high-speed interfaces will make possible, designers are naturally interested in learning more about these technologies.

Many designs, however, use 16-, 32-, or 64-bit buses running at tens of megahertz between chips or boards. Although commonplace and frequently not subject to any compelling pressure for faster throughput, there are nevertheless many reasons why designers are choosing to serialize these parallel links—albeit at lower data rates than those used for high-throughput systems.

Common challenges that designers face with the traditional parallel bus approach include managing skew, noise immunity, high power, and the limits on scalability. The serial-based approach offers solutions to these challenges, making it more attractive in many situations.

  • Moving to a serial link limits the number of signals to be transmitted across the link. In turn, this allows the use of differential interfaces such as LVDS. By their nature, these provide better noise immunity, lower power, and lower emissions than the LVCMOS signaling most common for parallel interfaces.
  • Serial links use SERDES technologies, which embed the clock in the data. This relieves system designers from having to manage critical clock-to-data skews. But SERDES design is not easy. The toughest timing and design issues can be tackled once by the SERDES chip designer, though, rather than encountered repeatedly in every system that is developed.
  • Serial-based approaches limit the number of traces on circuit boards, conductors in cabling, and pins in connectors. True, these run at higher speeds than those for the typical parallel bus. However, thanks to leading-edge communications and networking advances, the connectors, materials, and design techniques are now sufficiently advanced such that hooking up a 1-Gbit/s link should be within the capability of most system designers.

Over the next few years, acceptance of serial technology should continue to increase. Initially, the high cost of SERDES chips limited their use to high-performance applications. Designers were unlikely to adopt it despite its technical elegance. Today, lower-speed SERDES chips are available at less than $2.00 per TX/RX pair, virtually eliminating this economic roadblock.

Designers from a broad swath of industries, from industrial to consumer and from military to communications, are investigating, implementing, and realizing the benefits of low-speed serial links. Some of the standards for lower-speed SERDES indicate the breadth of this adoption. Examples include the SMPTE 292M and 259M standards in video broadcast applications, GbE in routers, the continued use of lower-end Sonet standards (OC-3 and OC-12), the emerging CPRI and OBSAI wireless basestation standards, 1G/2G Fibre Channel, and Serial ATA in the storage space.

This quiet adoption perhaps deserves more attention in the press. More importantly, it merits the attention of designers creating their company's next-generation products. Don't be surprised if this "quiet" adoption starts to get noisy.

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