A development kit for M-Modules and PMCs (PCI mezzanine cards) transforms specialized I/O requirements into a series of standardized products. The kit, from MEN Micro Inc., uses a concept that the company calls Universal Submodule (USM) to implement a board’s desired functionality through one or more IP cores in an FPGA. The USM simply plugs into the respective base mezzanine, allowing functionality to be changed at any time by changing IP cores. The corresponding line drivers are located on the USM, while its Nios soft core processor is implemented on an Altera Cyclone II FPGA to provide local intelligence where needed. I/O signals are routed through a front-end SCSI connector. The same USM may be used on M-Modules, PMC modules, XMCs and conduction-cooled PMC modules. Product development is limited to the USM module and the FPGA content, significantly speeding time to market.
The kit includes a base M-Module (an M199 equipped with an FPGA, 32 Mbytes of DRAM, and 8 Mbytes of flash) or a base PMC module (a P599 equipped with an FPGA, 32 Mbytes of DRAM, and 2 Mbytes of flash). The kit also provides a wire-wrapped USM plug-in module; a test board that receives I/O signals from the FPGA and that enables the implementation of a debug interface for the Nios processor; and a SCSI cable to connect the base module and test board. The included FPGA package is comprised of the Nios processor, memory control, and bridges that connect the PMC or M-Module to the Avalon or Wishbone bus. For IP cores on the standard Wishbone bus, MEM Micro’s Wishbone Bus Maker tool is included. For the Avalon bus, Altera's Quartus II design environment, including the SOPC builder, is required to use the Nios cores and to develop IP cores.
Delivery is within four weeks.
The complete development package (with either an M-Module or PMC base board) costs $2654.
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