EE Product News

Mainstream PLDs Moved Into Smaller, Higher-Pin-Count Packages

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With the development of new packaging technology, board space requirements have been dramatically reduced and pin counts—and therefore I/O counts—substantially increased for the firm’s mainstream programmable logic devices. The new PLD housing includes: 144- and 280-ball, 0.8-mm pitch chip-scale packaging for the SpartanXL FPGA and XC9500 CPLD families; 1.0-mm FinePitch BGA packages with 256 to 680 balls for Virtex FPGAs; and a 144-ball chip-scale package for two small Virtex devices. In lowering power dissipation and form-factor size, the new chip-scale package (CSP) is particularly well-suited for use in digital modems DVDs, camcorders, and other high-volume, cost-sensitive applications. The CSP is said to be the first for FPGAs that meet JEDEC Level 3 moisture sensitivity requirements. The FinePitch BGAs’ 1-mm pitch contacts compare to the 1.27- and 1.5-mm of conventional BGAs, reducing by more than half board space requirements and offering up to 512 user I/Os.

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