Portable health appliances and services are becoming ubiquitous. Constantly on, they must be efficient and "invisible." This brings new challenges regarding low power consumption and small size. Waferlevel chip-scale packages (WLCSPs) now enable medical treatments that were previously impossible to implement.
These new applications include invasive sensing, medical implants, and disposable, portable monitors. But to get the most out of WLCSPs in terms of performance and reliability, designers should heed the best practices in designing the printed-circuit board (PCB) land pattern, pad finish, and board thickness.
Wafer-level chip-scale packaging is a variant of the flip-chip interconnection technique (Fig. 1). With WLCSPs, the active side of the die is inverted and connected to the PCB using solder balls. The size of these solder balls is typically large enough (300 µm pre-reflow for 0.5-mm pitch and 250 um pre-reflow for 0.4-mm pitch) to avoid the underfill that is required for flip-chip interconnects. This interconnection technology offers several advantages.
First, considerable space savings are obtained by eliminating the first level package (mold compound, lead frame, or organic substrate). For example, an eight-ball WLCSP occupies only 8% of the board area taken up by an eight-lead SOIC. Next, inductance is reduced and electrical performance is improved by eliminating the wire bonds and leads used in standard plastic packages.
Also, designs yield a lighter weight and thinner package profile, due to the elimination of the lead frame and molding compound. No underfill is required, as standard surface-mount (SMT) assembly equipment can be used. And finally, high assembly yields result from the selfaligning characteristic of the low mass die during solder attachment.
PACKAGE CONSTRUCTION
WLCSPs can be categorized into two construction types: direct bump and redistribution layer (RDL).
A direct-bump WLCSP consists of an optional organic layer (polyimide), which acts as a stress buffer on the active die surface. The polyimide covers the entire die area except for openings around the bond pads. An under-bump metallurgy (UBM) layer is sputtered or plated over this opening. The UBM is a stack of different metal layers serving as diffusion layer, barrier layer, wetting layer, and antioxidation layer. The solder ball is dropped (which is why it's called ball-drop) over the UBM and reflowed to form a solder bump (Fig. 2).
RDL technology allows a die designed for wire bonding (with bond pads arranged along the periphery) to be converted into a WLCSP. In contrast to a direct bump, this type of WLCSP uses two polyimide layers. The first polyimide layer is deposited over the die, keeping the bond pads open. An RDL layer is sputtered or plated to convert the peripheral array to an area array. The construction then follows the direct bump, with a second polyimide layer, UBM, and ball drop (Fig. 3).
Post ball-drop, the wafers are backgrind, laser-marked, tested, singulated, and tape and reel. There is also an option of applying a backside laminate after the back-grinding process to reduce die chipouts induced during sawing and to ease the handling of the package.
BEST PCB DESIGN PRACTICES
The critical board design parameters are pad opening, pad type, pad finish, and board thickness. Based on the IPC standard, the pad opening equals the UBM opening. The typical pad openings are 250 µm for a 0.5-mm pitch WLCSP and 200 µm for a 0.4-mm pitch WLCSP (Fig. 4).
The solder mask opening is 100 µm plus the pad opening. The trace width should be less than two-thirds of the pad opening. Increasing the trace width can reduce the stand-off height of the solder bump. Hence, maintaining the proper trace width ratio is important to ensure the reliability of the solder connections. For board fabrication, two types of pads/land patterns are used for surface-mount assembly (Fig. 5):
• Non-solder-mask defined (NSMD): The metal pad on the PCB (to which the I/O is attached) is smaller than the soldermask opening.
• Solder-mask defined (SMD): The solder mask opening is smaller than the metal pad.
Because the copper etching process has tighter control than the solder-mask opening process, NSMD is preferred over SMD. The solder-mask opening on NSMD pads is larger than the copper pads, allowing the solder to attach to the sides of the copper pad and improving the reliability of the solder joints.
The finish layer on the metal pads has a significant effect on assembly yield and reliability. The typical metal pad finishes used are organic surface preservative (OSP) and electroless nickel immersion gold (ENIG). The thickness of the OSP finish on a metal pad is 0.2 to 0.5 µm. This finish evaporates during the reflow soldering process, and interfacial reactions occur between the solder and metal pad.
The ENIG finish consists of 5 µm of electroless nickel and 0.02 to 0.05 µm of gold. During reflow soldering, the gold layer dissolves rapidly, followed by reaction between the nickel and solder. It is extremely important to keep the thickness of gold below 0.05 µm to prevent the formation of brittle intermetallic compounds. Standard board thicknesses range from 0.4 to 2.3 mm. The thickness selected depends on the required robustness of the populated system assembly. The thinner board results in smaller shear stress range, creep shear strain range, and creep strain energy density range in the solder joints under the thermal loading. Hence, the thinner buildup board would lead to a longer thermal fatigue life for solder joints.1
TESTING AND ASSESSMENT
In conjunction with the aforementioned variables, WLCSP reliability is assessed by subjecting the device to accelerated stress tests such as high-temperature storage (HTS), highly accelerated stress testing (HAST), autoclave testing, temperature cycling, high-temperature operating life testing (HTOL), and un-biased highly accelerated stress testing (UHAST). In addition to thermo-mechanical induced stress testing, mechanical tests such as drop and bend testing are also carried out.
HTS testing is performed to determine the effect of long-term storage on devices at elevated temperatures without any electrical stresses applied. This test assesses the long-term reliability of devices under high temperature conditions. The typical test conditions are 150°C and/or 175°C for 1000 hours, respectively. This test consists of exposing the parts at the specified ambient temperature for a specified amount of time.
HAST evaluates the reliability of nonhermetic packaged solid-state devices in humid environments. It employs severe conditions of temperature, humidity, and bias that accelerate the penetration of moisture through the package. Conditions include 130°C temperature, 85% relative humidity (RH), 32-PSI pressure (typical), and 96-hour duration. Autoclave testing uses extreme conditions of temperature, humidity, and pressure, similar to HAST. The only difference is that devices are not biased during this test.
The objective of temperature cycling is to determine the package's resistance when it's exposed to extremes of high and low temperatures and to detect the effect of alternate exposures to these extremes. A failure resulting from this cyclic thermo-mechanical loading is known as a fatigue failure, so temperature cycling primarily accelerates fatigue failures. The thermo-mechanical stress-causing fatigue failures are induced due to the difference in the coefficient of thermal expansions. Typical test conditions include 500 cycles at –65°C to 150°C or 1000 cycles at –55°C to 125°C.
HTOL or steady-state life test is performed to access the reliability of devices when exposed to high-temperature conditions over an extended period. It subjects the parts to a specified bias for a specified duration at a high temperature. The test conditions are 1000 hours at Tj = +125°C or 750 hours at Tj = 135°C or 500 hours at Tj = 140°C. Electrical test occurs at 168 and 500 hours and at end of test.
UHAST assesses a product's ability to withstand severe temperature and humidity. It is used primarily to accelerate corrosion in the metal parts of the product, including the metallization areas on the surface of the die. The test vehicles were preconditioned prior to the testing, which simulated the customer's board-mounting process.
The test normally consists of a bake to drive out the moisture inside the packages, a soak to drive a controlled amount of moisture into the package, and three cycles of IR or vapor reflow. Preconditioning includes 24-hour bake at 125°C +30°C/60% RH soak for 96 hours plus three times reflow at 240°C peak temperature. The stress conditions include 131°C/85% RH for 96 and 192 hours.
Today's customers demand electric products that are smaller, faster, and cheaper. WLCSPs can meet these demands. Furthermore, this technology is more widely used in portable products. Because portable products are more likely to be dropped than get affected by changes in the thermal conditions, the emphasis of reliability research is shifting to mechanical shock testing such as drop test and bend test.
Drop test, which is classified by the input acceleration or impact pulse (peak acceleration and peak duration), is a function of drop height, friction of guiding rods, strike surface, and felt materials. The typical test condition used is a peak acceleration of 1500 G, with an impact pulse of half sine and a pulse duration of 0.5 ms.
During each drop, the accelerometer fixed on the base plate performs the realtime measurement of the shock pulse. This ensures that the input pulse remains within the specified tolerance. Also, a strain gauge measures the dynamic strain response induced in the PCB during the impact. And, the drop test includes in-situ electrical monitoring of solder balls.
Bend tests provide a simple way to evaluate the quality of materials by their ability to resist cracking or other surface irregularities during one continuous bend. The test conditions include 1-Hz cyclic frequency and sine wave with a recommended test duration of 200,000 cycles or until at least 60% of all units have failed.
AN INSTRUMENTATION AMP LAYOUT
An instrumentation amplifier in a WLCSP can be be used to delineate wafer-level chip-scale PCB best practices. The AD8235 40-µA micropower instrumentation amplifier is popular for portable medical applications. Its miniscule size and ultra-low power consumption are effective for power-efficient and portable, lightweight medical devices and consumer-health products.
The objective is to specify PCB thickness and design the patterns to minimize the package stress, which can change offset voltage, gain accuracy, and common-mode rejection on an instrumentation amplifier. The AD8235 is mounted in the center of the PCB. The board stress (thermal and mechanical) is minimal at the center of the PCB and increases as we move toward the edge.
At 1.6 by 2.0 mm, the AD8235 experiences less die stress than larger WLCSPs. Its thin, 0.8-mm PCB also reduces stress because it is more pliable. It complies with the die during thermo-mechanical stress induction. And when the PCB warps, the AD8235 is soldered onto a small proportion of the surface area.
The area under the AD8235 experiences minimal bending compared to the rest of the PCB. This is further complemented by the trace width being kept to two-thirds of the pad-opening diameter. Maintaining this ratio ensures that the solder bump is not completely wicked onto the trace, so the package remains firmly attached to the board with a reasonable stand-off height. ENIG pad finishing is selected with less than 0.05 µm of gold to ensure a reliable solder joint formation.
REFERENCE
1. John H. Lau and S.W. Ricky Lee, "Effects of Build-Up Printed Circuit Board Thickness on the Solder Joint Reliability of a Wafer Level Chip Scale Package (WLCSP)," IEEE Transactions on Components and Packaging Technologies, Vol. 25, No. 1, March 2002, pages 3-14.
MIKE DELAUS manages the Wafer-Level Package Development Group at ADI. He received his BS in materials science engineering from the Massachusetts Institute of Technology.
SANTOSH A. KUDTARKAR is a package development engineer with analog Devices' Worldwide Manufacturing group. He holds a BE in electronics engineering from the University of Mumbai, India, an MS in electrical and mechanical engineering, and a PhD in systems science from the State University of New York at Binghamton.