The emergence of PLDs that integrate embedded processor cores as well as on-chip memory and peripherals has created modeling requirements that must be addressed. Advancements in PLD size, speed, and complexity by themselves aren't sufficient to enable system-on-a-programmable-chip (SoPC) design for the masses.
The accessibility of easy-to-use embedded processor cores and other IP for system-level functions is essential. It will allow flexibility and time-to-market advantages not possible with ASICs. Using predesigned cores that can be easily instantiated and simulated within an SoPC design speeds the overall design process by eliminating lengthy internal development or securing third-party IP licenses.
Whether a processor is a soft synthesizable core or a hard macro will affect the eventual performance, size, and power specifications of the final design. Each implementation approach will have its own design-flow requirements. One of the main advantages of using PLDs is that they provide a hardware platform on which it's possible to perform software development, modeling, system-level simulation, and co-verification very early in the design process.
A basic requirement for designing with embedded processors is the access to a cycle-accurate instruction set simulator (ISS). Many times, ISSs are available for standard embedded processor cores, like those offered by MIPS Technologies and ARM Ltd. Examples include execution-driven simulators that execute instructions and model their performance in a particular application, or event-based simulators that can provide performance statistics, profiling, and trace files containing cycle-by-cycle information about the instructions. But, ISSs may not be fast enough for certain applications. In those cases, actual processors in hardware evaluation boards might be employed for debugging via their debug ports.
To solve system-level problems optimally, it's important to have accurate and complete models of how a processor core interacts with memory, other devices, and I/O units. Designing with a hard-core processor often requires a bus functional model of the processor. This describes the particular system bus operations, timing, and interface to the other blocks within an SoC design. When designing with a soft-core processor, it also is necessary to have the right behavioral models to verify that the processor subsystem timing specifications are being met in the actual physical PLD implementation. Access to VHDL or Verilog simulations of the entire PLD-based SoC design, behavioral simulation, and support of VHDL and Verilog test benches are necessary too.
Offering both hard- and soft-core solutions is Altera's Excalibur Nios processor. These solutions are MIPS- and ARM-based. They integrate the processor, peripheral logic, and single- and dual-port memory into a "stripe," which is adjacent to a PLD structure. Industry-standard hardware development tools for design entry, simulation, and synthesis, plus a cycle-accurate model of the stripe, allow it to be simulated together with the PLD logic.
Contributed by Anna S. Chiang, Director of Marketing, Excalibur Business Unit, Altera Corp.