What's the point of having the hottest high-performance chip available when it doesn't fit on the board? We've all heard horror stories about chips not meeting timing closure or not working when they're back from the fab. What's often been overlooked is the chip that doesn't fit the package. Many chip designers assume it's the package designer's problem—he or she will make it fit. At one time, that was quite possible. But in today's world of increasing complexity and submicron technology, that assumption just isn't viable.
In fact, IC package design in conjunction with chip design remains a huge problem with few automated solutions. Many chip designers rely on spreadsheets for optimization decisions. And, the problem spans multiple boundaries within system design, from die to package and package to printed-circuit board (PCB).
What's caused this? Like much of the electronics market, the packaging problem grew faster than the ability of the EDA community to keep pace and develop solutions for chip designers. The headlong rush to miniaturization to meet the needs of the insatiable personal technology market has further complicated the situation. This, in turn, has created the need for other technologies, such as system in package (SiP) and 3D packaging with stacked dies.
Another cause is escalating complexity, which has left designers unable to handle these optimizations and tradeoffs with a level of confidence that ensures timely, first-pass success. Traditional methods are no longer adequate as designs grow larger and denser with more pins, feature higher I/O speeds and power, and use multiple voltage domains plus blends of analog and digital technologies. On top of that, market pressures have never been greater, requiring designers to do more with less.
What's needed to address the problem and make use of the promising packaging technologies is software to enable package-aware chip design. This will allow chip designers to assess packaging tradeoffs early in the design process.
Successful deployment of a chip includes design optimization and tradeoffs that reflect the different environments in which signals propagate. These include the die itself, the package substrate, and the PCB. What's needed, then, is software that lets the die be designed within the context of the external environment. This software should be able to accept various constraints from diverse design domains, including PCB, package, and IC. It should be able to optimally place I/Os as well as the required associated logic. It must produce the package bumps for attachment to the PCB, the routing on the top layer from I/Os to those bumps, and then be able to synthesize the bump patterns to achieve timing closure. It should also account for signal-integrity requirements. Developing such a solution for full chip integration early in the design, plus being able to simultaneously visualize the chip in the package, ensures design convergence. It would give chip designers iteration-free verification when the design is finally done and eliminates the ad-hoc approach to chip-package design.
With packaging playing an increasingly important role for chip designers, an automated solution that enables early analysis, optimization, and interconnection synthesis is a critical requirement. The result will be reduced time to market, flexibility for last-minute changes, and improved die and package designs with lower cost.
Kaushik Sheth can be reached at [email protected].