Electronic Design

Multichip Memory Combines NAND Flash And DDR DRAM

A three-die memory-centric multichip package (MCP) can lower cost and save valuable pc-board space in wireless handsets. The MCP contains a pair of 256-Mbit NAND flash memory chips and a low-power 256-Mbit mobile double-data-rate (DDR) SDRAM that can all operate from a 1.8-V supply. The DDR SDRAM can transfer data at up to 200 Mbits/s (per pin), which is twice as fast as conventional SDRAMs used in current handsets. The MCP also offers a single footprint, irrespective of DRAM type (DDR or SDR), DRAM density, DRAM data bus width, NAND density, and NAND data bus width. This streamlines handset board design. The NAND flash has been optimized via controller and chipset firmware to boot up handsets, eliminating the need for NOR devices in the design. The mobile DDR device's internal temperature-compensated self-refresh circuit automatically adjusts the self-refresh cycle as temperature changes, minimizing power drain and maximizing the battery life. Samples of the MCP memory are available now.

Samsung Semiconductor Inc.
www.samsungsemi.com;
(800) 423-7364

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