Electronic Design

Network Search Engine Hums With Dual LA-1 Ports

Able to perform 266 million searches/s, the Ayama 20000 NSE uses dual LA-1 ports to divvy up the tasks between two NPUs for faster throughput.

Thanks to two LA-1-compatible interface ports, the Ayama 20000 network search engine (NSE) can break through tough data-transfer bottlenecks as well as expand network processor headroom. The NSEs support commercial network processors, including Intel's IXP2400, 2800, and 2850, and Applied Micro Circuits Corp.'s (AMCC) nP3700.

Dual LA-1 ports enable designers to split tasks between two NPUs, one for ingress and one for egress. According to Cypress Semiconductor, they're the only NSEs that can cascade ternary-CAM-based (TCAM-based) and algorithmic solutions. As a result, the search solution delivers very high performance for IPv6 applications at comparatively minimal cost.

Available with 9 or 18 Mbits of on-chip memory, the Ayama 20000 search engines can perform up to 266 million searches/s. The 9-Mbit version can hold up to 256k entries, while the 18-Mbit version doubles the number of entries. In addition, the chips include the company's unique Key Capture logic. Thus, designers can reuse portions of the search key, which conserves LA-1 port bandwidth. Each LA-1 port can handle up to 128 contexts and special age-assist tables to provide aging support (256k entries) for up to four tables.

Other features include an associative data manager. It optimizes the on-chip SRAM capacity by removing empty address space caused by wide entries, particularly for IPv6 addresses. In addition to the LA-1 ports, the main fast-link cascade bus interface on the Ayama 20000 chips allows the NSEs to connect to Ayama 10000-series NSEs for TCAM searches, as well as to the company's Sahasra 50000 NSEs for algorithmic searches.

The Ayama 20000 also supports an out-of-band interrupt-driven Result-Available Vector. This can save polling cycles for result retrieval.

Physically, the pin layout on the 1152-contact, 35- by 35-mm BGA package permits board designers to mount two quad-data-rate SRAMs on the flipside of the board in a "clamshell" format. The setup reduces routing complexity and minimizes the board space required for the subsystem. Able to perform associated data lookups for the network processor by accessing the external SRAM, the Ayama 20000 generates 24-bit wide SRAM addresses, and 32 bits are returned for each read access. The chip's core logic operates from a 1.2-V supply, while the I/O pins are compatible with 1.5-V HSTL and 2.5/1.8-V low-voltage CMOS circuits.

For software development, Cypress offers the Cynapse development platform. Among its components are reference applications, diagnostic code, application programming interfaces, simulation models, and device drivers. Also contained within the full reference design kit are development boards, data-plane macros for standard network processors, and Verilog, IBIS, and BSDL models. On top of that, a complete set of application notes will help speed time-to-market for routers, layer 2 and layer 3 switches, CMTS, DSLAM, and storage-area-network systems.

When it comes to Intel-based NPUs, Cynapse provides full interoperability on the IXDP2400 development platform. Cypress also supplies the foreign object model for integration. Similarly, for AMCC NPUs, Cypress offers a daughtercard that plugs into the nP3700 development kit and a reference design kit to accelerate product design.

Samples of the Ayama 20000 NSE are immediately available. In lots of 10,000 units, the 9-Mbit version sells for $175, while the 18-Mbit version costs $325.

Cypress Semiconductor Corp.
www.cypress.com

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