Hardware-based verification systems have seriously outgrown their reputation of a few years ago. They are no longer those behemoth boxes that sit in the corner of the lab for use only by a select few. They are becoming much more widely available and user-friendly — and not just for those that can afford such verification horsepower. The newer systems today are much more versatile verification systems that can be leveraged across the entire design and verification teams. These systems are not just raw performance or hardware boxes populated with the latest FPGA chips — in fact, this could not be further from the truth.
Unlike many of the prototyping boards on the market that are populated with the latest FPGA chips, the features you will see in these new systems eliminate the need to combine many independent tools and manual interventions to build time-consuming custom verification systems. These systems offer complete simulation acceleration and emulation solutions in one. You will also find that the software environments that come with the hardware integrate HDL compilation, design partition, FPGA compilation, and runtime simulator binding all through one common database.
In other words, these systems today offer the only simulation acceleration and emulation combination with the ability to provide dynamic state-swapping-and-continuation between the hardware logic-emulation engine and the software simulation engine. The actual hardware "box" in many ways has become transparent to users. The advantages of hardware can be accessed just as if it were the software simulator they were most comfortable and familiar with.
Scalability Wears Many Hats
The speed and capacity scaling of these newer hardware offerings are much like PC systems. The speed and the memory capacity of PC systems scale with the advances of microprocessor and DRAM technologies to meet the ever-increasing demand in general computing applications. These newer hardware systems scale with the advances of FPGA technology in both speed and gate-count capacity to meet the ever-increasing demand in simulation acceleration and emulation applications.
Speed and gate-count capacity improvements continue to rise dramatically over earlier generations simply by using the latest FPGA technology. And like PC systems, all these improvements stay within a much easier to manage form factor and power requirement. So these new usage models offer ease of installation within your basic working environment.
The underlying technology for hardware-based verification systems has really taken huge steps by offering unique system architectures, such as reconfigurable computer (RCC) technology. So these machines are not hard-wired into a high-speed parallel logic evaluator just to model the design objects. Instead, they tend to be configured into massively parallel behavioral processors with a concurrent event synchronization mechanism to govern the system execution.
With this architecture, design teams can model not only the RTL design objects but also the behavioral verification objects for total verification acceleration. It is important to know that certain event-driven control mechanisms are a key factor for behavioral modeling because the executions of behavioral objects are runtime dynamic and event-driven in nature. It is hard to execute these objects efficiently on hard-wired logic evaluation engines that require static scheduling of all the operations at the compile time.
In the past, RTL objects have been mapped into these systems, while leaving the behavioral verification objects in the software simulator. Due to the limit in gate and memory capacity of older FPGA chips, this has been a balanced strategy to manage overall system complexity. As the FPGA gate count and memory capacity has doubled in the newer systems, it has become practical to map behavioral verification objects into the hardware for the next level of performance gain.
Outgrowing The Simulation-Only Past
In the past, we have seen that leaving verification objects in the software simulator could create a performance bottleneck in some applications. The newer behavioral processor-compiler technology in today's hardware verification systems significantly improves the performance of these applications by mapping behavioral verification objects automatically into the behavioral processors.
Mapping assertion statements through static assertion synthesis can easily create finite state machines with exponential number of states that could not fit into the hardware before. With the use of behavioral assertion processors and block memories to manage dynamic state expansions, it becomes practical to map all SystemVerilog assertion statements into the hardware.
It is time to move on and take a good, hard look at verification systems that really can help designers get their products out on time with the least amount of effort to full block and system-level verification closure. Teams need new solutions that build upon a familiar infrastructure but tap into these extremely powerful acceleration and emulation engines.