A fourth-generation network-search-engine (NSE) architecture accelerates Internet Protocol version 6 (IPv6) operations and enables value-added services in 10-Gbit/s applications. Initial products based on this architecture, developed by Integrated Device Technology, will permit up to 1 billion searches/s (BSPS), which is four times the capability of existing solutions.
Based around a ternary CAM core, the architecture can support a base search width of 80 bits. According to IDT, this optimizes the NSE architecture to create future products that efficiently support IPv6 as well (see the figure). Error checking and correction (ECC) also has been implemented in the architecture, a feature never before implemented in an NSE.
The ECC logic addresses potential soft errors, ensuring data integrity and compliance with stringent service level agreements (SLAs). These soft errors can cause a system to malfunction or act unpredictably, which is unacceptable in high-reliability networking equipment. By automatically checking and correcting impacted code before it can affect functionality, devices based on this architecture will help maintain consistent system operation.
The quad simultaneous multi-database lookup (SMDL) feature pushes performance up to 1 BSPS by supporting four simultaneous lookups in one cycle with a core search rate of 250 million searches/s. The 80-bit base search width efficiently supports IPv6 by offering a 320-bit search width to accommodate a 296-bit wide IPv6 five-tuple lookup, optimizing the database size for those operations. A 40-bit interface-mode option simplifies designs and lowers costs by reducing the number of ASIC pins and additional signals routed on the boards.
Initial NSE products based on the fourth-generation IDT architecture will be available in the first quarter of 2005. They're expected to include a high-speed transceiver logic (HSTL) interface to ASICs and FPGAs.
Integrated Device Technology