As CDMA technology continues to wind its own way through the cellular diaspora, it is as susceptible to the pressures of increased integration as any of its counterparts. The reasons are myriad, but they mostly revolve around the almost universal needs to conserve board space, decrease power consumption, improve signal integrity, reduce cost, and speed time-to-market.
Well aware of the advantages of high integration, LSI Logic Inc. has developed the first completely integrated baseband processor for CDMA applications. The chip, dubbed the CBP 3.0, is fully IS-95b compliant. It also includes all the mixed-signal, modem, digital processing, and voice-codec functions on a single slab of silicon.
Based on the company's G11 CMOS process, which features 0.18-µm (L-effective) line widths and an operating voltage of 1.8 V, the CBP 3.0 incorporates two OakDSPCores—one for modem assistance, and one for vocoder operations. Meanwhile, an ARM7TDMI processor acts as a central control processor. The device is supported by the company's CoreWare building blocks, which allow the quick addition of a wide range of telephone/computing capabilities.
The end result is a turnkey baseband solution with standard RF/IF interfacing that simplifies the selection of the remaining components required for a complete device. Depending on those components and the mode of operation, the CBP 3.0 permits development of CDMA cellular telephones with up to 300 hours of standby time and two hours of talk time. The device comes complete on a 280-pin CSP that measures 16 by 16 mm.
Originally developed by Qualcomm for military applications, code-division multiple-access (CDMA) technology has only flourished in the last three or four years. Popular in Asia (particularly in Japan and Korea, as well as China), Latin America, and now North America, CDMA tripled its subscriber base between 1997 and 1998. And, it's expected to surpass the 50 million mark this year. While Global Systeme Mobile (GSM) technology has a much higher numeric penetration, CDMA continues to hold the advantage in terms of current and predicted percentage growth— and for good reason.
According to the Telecommunications Research and Action Center (TRAC), Washington, D.C., CDMA outperforms other digital and analog technologies on every front, including signal quality, security, power consumption, and reliability. Analog came out ahead overall for availability.
CDMA's key attributes are its flexibility, system capacity, quality of service, and implementation economies. In terms of flexibility, the IS-95 standard allows service providers to allocate data in 8-kbit/s increments within the CDMA channel's 1.25-MHz bandwidth, based on how providers configure software download to already installed network controllers.
This enables operators to implement return data speeds at rates much lower than 64 kbits/s, extending the handset's battery life. An improved coding-gain/modulation scheme, voice activity, three-part sectorization, and spectrum reuse in every cell and all sectors give CDMA the advantage in capacity, as well.
The quality-of-service advantage is significant. It results almost entirely from CDMA's spread-spectrum modulation scheme. Where other narrowband systems can suffer severe degradation at the hands of multipath fading, CDMA actually benefits.
Using RAKE receivers and other signal-processing techniques, each mobile station selects the three strongest multipath signals and coherently combines them to produce an enhanced signal. Also, soft handoff eliminates the ping-pong effect mobile users suffer when passing over cell borders. As for economics, CDMA requires fewer cell sites and no costly frequency reuse pattern. Additionally, the average transmitted power is lower, thereby extending the average battery life.
One of CDMA's major advantages, though, is actually a result of its technical merits. CDMA has been selected as the scheme of choice for the greatly anticipated third generation (3G) of mobile telephones. The 3G cdma2000 uses a CDMA air interface, based on the existing IS-95B standard, to provide wireline-quality voice service and high-speed data services at rates ranging from 144 kbits/s for mobile users to 2 Mbits/s for stationary users.
Despite the activity surrounding CDMA, the fact that GSM has by far the larger portion of the subscriber pie cannot be ignored. Many RF and digital IC companies still devote the bulk of their efforts toward cementing their standing in that area, though they are now beginning to set their sights on the CDMA alternative.
Regardless of the modulation scheme, the ideal situation from a purely integration point of view (disregarding the loss in flexibility it would entail) would be to have the complete RF and baseband processing sections on a single substrate. Unfortunately, differences between the processes required to implement the two make a single-chip solution more of a goal than a realistic alternative right now.
RF And Baseband Still Separate
As things stand today, the RF and baseband sections remain separate entities with their own rules and codes of behavior. The RF end strives for complete integration in and of itself, using techniques such as low IF or direct conversion (zero-IF) to either lower the size and cost of IF filtering components or eliminate the need for them altogether.
The system's baseband section typically remains a two- or three-chip solution. One chip handles the mixed-signal processing, another handles the digital signal processing, while the third takes care of voice codec functions. Such levels of separation prevent the baseband functions from taking more advantage of the advances in digital CMOS integration that could lead to lower overall cost and ease of manufacturing. But that situation may well be changing.
LSI Logic is paving the way to change with its vast experience in integration and system-on-a-chip ASICs and CoreWare solutions. Based on its leading-edge G11 CMOS process, the company's CBP 3.0 CDMA baseband processor is the first device to integrate all three baseband functions onto one chip (Fig. 1). The chip expands upon the CDMA baseband processor 1.75 architectural plan announced last year, with a notable addition. The receive-channel filtering, traditionally completed off chip due to integration difficulties, has been incorporated into the single-chip design. This is crucial. Other manufacturers also have achieved highly integrated baseband solutions, but they haven't been able to include the filtering on board.
The processor itself is partitioned into two sections—the analog subsystem, and the digital core. The digital core contains the dual OakDSPCores and the ARM7TDMI microprocessor. One DSP handles the modem functions, while the other takes care of vocoder operations. Both DSPs run at 39.3216 MHz. The ARM7 runs at the same frequency and executes the protocol stack, the man-machine interface, searching, automatic gain control (AGC), and automatic frequency control (AFC) functions.
The digital section communicates with the analog subsystem through a digital interface that controls the baseband codec, voiceband codec, and ancillary functions. A sine-wave squarer feeds the phase-locked loop (PLL) from an external, small-signal, 19.2-MHz clock reference. This generates the primary clock of 39.3216 MHz, as well as divided-down versions. The squarer is a bandpass comparator that rejects high-frequency noise above 50 MHz and low-frequency noise below 1 MHz.
To reduce substrate noise effects, every output clock is fed into the analog circuits first and then to the rest of the digital chip. A time delay of even several nanoseconds prevents switching noise from the digital clocks from adversely affecting the analog sampled-data circuits.
The receiver channel filter is the key differentiating aspect of the CBP 3.0 (Fig. 2). Conventionally, filters are integrated through the use of switched-capacitor technology. While this is fine for transmitters, it has proven much too power hungry for receivers. The filter is on all the time, as it periodically has to check in with the base station. Therefore, a lower-power implementation is essential.
The alternative is a delta-sigma (Δ−Σ) filter, which is essentially an analog-to-digital converter (ADC) that has had its response modified so it acts as a filter. Fully integrated into the CBP 3.0 CDMA baseband processor IC, the Δ−Σ filter combines a traditional CDMA elliptic channel-select filter and a 4-bit ADC into a Δ−Σ modulator, followed by a digital filter. The high-dynamic-range Δ−Σ modulator converts the input signal and adjacent channel interference together into a bitstream. Then, the digital filter performs the decimation and channel selection using a digital elliptic filter.
The advantage of this approach is the achievability of lower power and smaller area, which results from the use of advanced, low-voltage, digital CMOS technology for the digital filtering, the elimination of filter tuning, and lower noise due to oversampling. While companies have tried this already, none has been able to integrate it on board.
Switched-Capacitor Transmit Filter
On the transmit side, the filtering was implemented in a switched-capacitor form. Since it is the transmit path, the power consumed by that particular filter is relatively small compared to the receive chain.
After the filter comes the ADC comparator, which uses a two-stage approach. The first stage is a four-input differential pre-amplifier, and the second stage is a regenerative latch connected to the first stage through samplers. This isolates the first stage from second-stage kick-back noise. The baseband transmitter comprises a 10-bit, 9.8-Msample/s, switched-capacitor digital-to-analog converter (DAC), followed by a 2X oversampled switched-capacitor filter (SCF) and a second-order reconstruction RC filter. Over-
sampling at the SCF eases the reconstruction-filter requirements, and a 2X ratio is chosen because the low-pass SCF conveniently places a zero at 9.8 MHz. This process rejects the images at 9.8 MHz while supplying sufficient rejection at other frequencies.
No Companding Required
The voiceband codec provides a CCITT G.711/712-compliant voice interface without companding. The OakDSPCore performs vocoder operations for QCELP-13 and QCELP-8 for North America, as well as EVRC for Asian markets. The codec uses SC second-order Δ−Σ front ends with a 2.6-MHz oversampling rate. The voice ADC path's decimated output is fed into a bandpass filter. This filter offers precise, in-band spectral shaping to eliminate signal energies below 300 Hz and above 3.6 kHz for proper speech compression.
After bandpass filtering and modulation in the voice DAC path, the bitstream data is converted into an analog signal using a 1-bit DAC. This is followed by a first-order SCF and a class A-B reconstruction filter that drives 600-Ω speakers.
While this describes the main signal paths, other features on board haven't been mentioned. These include auxiliary DACs, a real-time clock, on-chip RAM for the ARM7, two serial I/O channels, a keypad interface, an external-memory path, and interfaces for the display, speaker, and microphone . In fact, all that needs to be added for a complete solution is external and flash memory, the RF/IF stages, channel-isolation filters, and the RF low-noise and power amplifiers.
Keeping with the original goals of maximum flexibility, the CBP 3.0 leverages LSI's CoreWare design methodology and library of building blocks to help the customer achieve maximum product differentiation while minimizing time-to-market. Potential value-added functionality includes an infrared interface, a custom display interface, a USB interface, PDA functions, and hands-free voice recognition in the DSP or control processor. The device also is WAP-enabled and supports trimode operation.
The core operates off 1.8 V, while the mixed-signal circuitry operates down to 3.0 V. The device comes in a 16- by 16-mm CSP with a 1-mm profile and a 0.8-mm ball pitch.
A slew of software deliverables are provided with the chip. These include the DSP operating system, hardware drivers, vocoders and algorithms, and an IS-95B protocol stack from Isotel Inc. that includes source code. LSI Logic also makes available its ETS diagnostic software, its Graphical Analysis Tool, and third-party Design Verification Tool software.
Price & Availability
Pricing for the CBP 3.0, which is shipping now, is $35 each per 10,000 units.
LSI Logic Inc., 1551 McCarthy Blvd., Milpitas, CA 95035; Greg Helton, (408) 433-8000; [email protected]; www.lsilogic.com.