Electronic Design

One Smart Serial RapidIO Switch

This pre-processing Serial RapidIO switch reduces DSP cluster processing load by 20% or more.

Integrated Device Technology (IDT) takes a novel approach, or rather an intelligent approach, to Serial RapidIO (sRIO) switching. The company's 70K2000BR preprocessing switch (PPS) chip combines an sRIO switch with on-chip processing optimized for datastream manipulation.

The PPS typically will be used in stream processing applications such as 3G wireless basestations, where data must be manipulated and distributed for further processing—often using a DSP farm (Fig. 1).

Also, the PPS is an ideal partner for sRIO-capable DSPs, such as Texas Instruments' TCI6455 and TCI6482. These chips connect directly to the PPS. Direct connection reduces the system footprint, simplifies system design, and provides maximum throughput.

SMARTPROCESSING, SMARTSWITCHING
The PPS is able to handle up to 10 4x ports or 22 1x ports. It also can manage combinations of 1x and 4x ports. Each port is independently programmable for standard sRIO speeds of 1.25 Gbaud, 2.5 Gbaud, or 3.125 Gbaud.

Furthermore, each port can be configured for short-haul (chip-to-chip) or long-haul (backplane) transmission. This programmability enables the sRIO switch fabric to handle I/O, data distribution to local processing units such as the DSPs, and communication with off-board resources.

The PPS architecture uses programmable arbiters to connect the ports to the switch or to one of 10 pre-processing scenario (PPSc) units (Fig. 2). The PPSc units can process incoming packets and then reroute them to the desired destination in the sRIO fabric.

The independent PPSc units are programmable state machines that are typically configured upon system startup. Changes to the state machine can be made using the I2C interface or the JTAG interface, or in-band via sRIO.

The PPS approach provides modular expansion using standard sRIO links, while a more conventional approach would employ FPGAs and dual-port memory. It offers flexible packet manipulation without resorting to complex FPGA programming. Also, the PPS is a more limited preprocessor than an FPGA can be, but it can easily handle basic packet manipulation.

PACKET MANIPULATION
Pre-processing occurs in a PPSc as it receives sRIO packets. The PPSc can apply one or more operations to the data stream (see "PPSc Operations," p. 34). The type of operations will depend on the overall application. The PPS has a processing bandwidth of almost 100 Gbits/s.

The PPSc won't perform major transforms on the data—this is usually left to the DSP or CPU. But the PPSc can perform operations that are normally required, because the data source will provide information in a format that the processing chips can't process easily.

For example, data from a 12-bit analog-to-digital converter (ADC) may come packed in a packet that the PPSc converts to 16-bit data, which is more easily manipulated by a 16- or 32-bit DSP. Likewise, endian conversion allows a little-endian microcontroller to deliver data through the PPS, which then will be processed by a bigendian processor such as a PowerPC.

Splitting and redistributing data is common in wireless applications where an incoming signal contains information for multiple calls. The PPS summation functions can be used to support wireless output, too, by combining data from multiple calls that then are sent using a common antenna.

This symbol rate processing is the inverse of splitting incoming data. The same basestation usually completes both operations. With this approach, uplink and downlink operations can be combined on a single card.

The PPS architecture fits a wide range of applications that require reformatting and switching large amounts of data, like radar and medical image processing. It also permits a system to dynamically allocate resources. With the switching approach, designers can incorporate and migrate services throughout the system easily as well.

PRICE AND AVAILABILITY
Available in a 27- by 27-mm BGA-676 (ball-grid array) package, the 70K2000BR PPS chip costs $125. Maximum power dissipation is 10 W, but typical operation ranges from 3 to 4 W. Quantities will be available in October.

A MicroTCA evaluation board will be available with a PPS and four of Texas Instruments' TCI6455 DSPs (Fig. 3). IDT includes a graphical, Windows-based software tool that enables designers to run a wide range of simulations and system evaluations based on simplified RF and DSP card traffic models.

Integrated Device Technology www.idt.com

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