By stacking layers of storage on top of each other, Matrix Semiconductor has developed a family of one-time programmable (OTP) memories that deliver the industry's smallest and lowest-cost chips. The largest member in the Trinity family, a 1-Gbit device, measures just 31 mm2 and costs about 20% to 50% less than comparable-density flash memories.
This OTP memory family is based on the company's next-generation stacked-layer polysilicon-transistor memory cells implemented in a 150-nm process. The technology lets users field-program the cells in the storage arrays once.
This is similar to the concept used a few generations ago with fuse PROMs or windowless UV EPROMs. But with the much higher density levels, the layered memories can be used in digital film, music storage, electronic books, and many other applications.
The cells are one-time programmable. Yet by using a chip with more storage than needed for the application and then logically dividing the memory array into pages, users can effectively reprogram the chip by programming a new page of bits and logically swapping it for the old page.
The family is based on a new Segmented Word-Line (SWL) architecture that improves the density of the memory array by 23% over the checkerboard architecture used in Matrix's previous OTP memories. A base silicon chip holds the control and sensing circuitry and then stacks just two or four layers of storage cells on top of the base silicon. In addition to the 23% gain in density due to the SWL, additional density improvements in the base silicon reduce the size of the chip under the storage array layers (see the figure).
To make the most efficient use of process technologies, designers at Matrix will be able to use tighter design rules for the polysilicon storage array layers while maintaining slightly more relaxed rules for the silicon base chip. This will let them reduce manufacturing costs since masks for 150-nm design rules used on the silicon base chip cost less than masks for 130-nm rules used for the storage layers.
For the first generation of Trinity OTP memories, the silicon base chip will be fabricated using 150-nm design rules, while the memory array layers will use 130-nm design rules. In the next generation, Matrix expects to use 140-nm rules on the base silicon chip and 90-nm rules for the storage layers.
There initially will be four memory chips in the Trinity family—16-, 32-, 64-, and 128-Mbyte devices—each offering access times of 150 ns.