Electronic Design

Overvoltage-tolerant quad buffer used as voltage level shifter

The LCX standard logic product family was designed with overvoltage-tolerant inputs and outputs, enabling users to easily interface LVTTL and 5-V TTL buses. Because the LCX outputs are overvoltage-tolerant when disabled, system designers can take advantage of this overvoltage tolerance to design a nifty and inexpensive voltage level shifter. With all of the mixed voltage designs in the world today, there may be several different voltage interfaces or bridges required on a single board (e.g., 3 V to 5 V, 1.8 V to 3 V, etc.).

The MC74LCX125 is a quad buffer with overvoltage-tolerant inputs and outputs. Because each of the four bits have individual output-enable pins, they can be enabled/disabled separately. The LCX125 is enabled Low and disabled High.

The voltage-level-shift design is very simply implemented. Each of the LCX125 data inputs are tied to ground (Fig. 1 and Fig. 2). The outputs are tied to a chosen pull-up voltage (or various voltages) through separate pull-up resistors (values can be mixed or matched depending on desired speed/power requirements).

The output enable (—OE) inputs are substituted for the data inputs. When an —OE input is Low, the corresponding output is enabled (see the table). Since the input pin is tied to ground, the output is pulled Low (by the LCX125 output transistor). When the —OE input is High, the output is disabled and the pull-up takes control. Because the output is overvoltage-tolerant, the pullup voltage can be taken as high as 7 V (absolute maximum rating on a disabled LCX output) without causing any stress on the part or any unwanted loading at the interface.

Though LCX reliability with a disabled output isn’t guaranteed beyond 7 V, the LCX125 level shifter could actually function well beyond 7-V pull-up. The minimum recommended operating voltage is 2 V for an LCX part. Therefore, by using the MC74LCX125, level shifting can be accomplished for various power supplies and pull-up voltages from 0 to 7 V. The pull-up voltage can be greater than or less than the supply voltage. The supply voltage for the LCX125 should be kept between 2.0 and 5.5V. LCX is CMOS, so the VIH levels must be kept greater than 70% of VCC (1.4V min for VCC =2V). The minimum accepted input voltage is 1.4 V, while 7 V is the maximum input voltage. The outputs depend on the pullup voltage, and can be anything between 0 and 7 V.

Briefly mentioned above was the user’s ability to control the speed of the “propagation delay” from a Low level to a High level (it’s actually a Low to High impedance or tPLZ), and the amount of current through the pull-up resistor when the output is static Low. The speed of Low-to-High transition is based entirely on the RC load on the disabled output.

The higher the resistor value (and capacitance value), the longer the delay and lower the current. The lower the pull-up resistance, the faster the switch, but the static Low current increases. There is zero current in the case of a static High level, regardless of the pull-up resistance, so the design could be maximized based on that knowledge. The static output current (IOL) is simply the pull-up voltage (VPU) minus the static low voltage (VOL) divided by the pull-up resistor value (RPU): IOL = (VPU − VOL)/RPU.

The High-to-Low transition depends on the ability of the MC74LCX125 to quickly sink the IOL current. The LCX125 is specified to sink a minimum current of 24 mA (at VCC = 3 V). This is a static specification. The dynamic switching capability is much greater.

Testing of the ac parameters shows delays of about 9 to 11 ns for the tPLZ with a 250-W pull-up resistor and 50-pF load. The output is measured at 50% VCC, regardless of the VCC. The delay varied little due to the supply voltage or the pull-up voltage. The tPZL varies substantially with power supply voltage and pull-up voltage. The delay was faster at lower pull-up voltages and, of course, faster with an increase of supply voltage. Depending on the voltage conditions, the measured values are 2.4 to 11.8 ns. The 2.4-ns result was measured with VCC = 5.0 V and VPU = 1.5 V. The slowest delay was measured with VCC = 1.8 V and VPU = 6.0 V.

An MC74LCX125-based voltage level shifter application is flexible in design and easy to implement. The voltages, currents and propagation delays are almost entirely left to the discretion of the designer.

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