Electronic Design
Package Interconnects Can Make Or Break Performance

Package Interconnects Can Make Or Break Performance

Chip and package designers can select from a bewildering catalog of interconnect technologies. Interconnects between the die and package include traditional wire-bond and flip-chip solder bumps, flip-chip gold-to-gold and copper pillar technologies, and embedded technologies like embedded wafer-level ball-grid array (eWLB).

Within a package, die can be side-by-side, stacked, flipped piggyback on each other, or interconnected with the latest chip-to-chip interconnection—through-silicon vias (TSVs). Package-to-PCB (printed-circuit board) interconnect technologies include old standbys such as through-hole leaded devices, surface-mount leaded devices, area-array solder joints, leadless leadframe packages, and land-grid arrays. Each interconnect technology was developed to improve performance, reduce cost, or both.

Designers can sort through these many options by understanding the relative merits and demerits of each technology. Then they will be equipped to make the selection that best fits the need of the device being designed.

Periphery Vs. Area-Array Packages

Both leadframe-based peripheral interconnect and laminate substrate-based area-array packages are mature technologies. Array packages, as the name suggests, provide contact points in an X,Y array. Escape routing to a package’s periphery can be much simpler than routing to an X,Y array. This often makes for a less complex system PCB for peripheral leaded devices, with fewer routing layers. Area-array configurations, on the other hand, allow for much smaller packages for a given pin count. Most current systems use some combination of area-array substrate and leadframe-based packages.

The type of package selected will ultimately influence system-level reliability. Leaded packages have compliance that improves temperature cycling and drop test reliability, generally exceeding the performance of area-array packages. Package design and the interconnect technology within the package significantly affect electrical and thermal performance.    

Wire-Bond Interconnect

Wire bond, developed in the 1950s and 1960s, turned into a massively efficient, high-volume manufacturing technology that still maintains lots of traction today, years after industry pundits predicted its demise. Wire bonds offer flexibility to match different chips to standard leadframe and substrate designs, and they often are more cost-effective than flip-chip alternatives.

With wire bonds, the same chip can be assembled into different package form factors, giving end users flexibility to fit the package that best suits the system or assembly process technology’s needs. Wire bonds are usually limited to the chip’s periphery. When chips are very small or have a large number of I/O, the wire-bond pitch requirements can grow to the size of a die, pushing up costs.

The primary electrical deficit of wire-bond technology involves high wire inductance, which can limit signal speed. The signal speed of wire bonds can increase by placing return current wires in parallel with the signals to get near transmission-line capabilities. A rule of thumb, and rules of thumb never fit all cases, is that wire bond technology can work up to 0.5 to 1 GHz.

Other wire-bond technology limitations include difficulty in evenly distributing the power and ground across large die, and ensuring the power and ground is noise-free. In addition, gold wires are ceding ground to copper wires due to cost and the fact that copper is more conductive than gold.

Flip-Chip Interconnection

Flip-chip interconnection eliminates the two primary technical limits of wire bonding—it provides area-array interconnect and reduces interconnect inductance, which enables higher-frequency performance. Current flip-chip devices operate at around 25 GHz and can perform at this frequency across hundreds of differential I/O.

How do flip-chip interconnects reduce inductance? They’re usually no more than 30 to 200 mm long, compared to wire bonds that can be 3 to 4 mm long. Assuming the same inductance per unit length, flip-chip interconnects are easily 100 times less inductive.

Flip-chip technology also allows all bonds to be made simultaneously, dramatically decreasing the time required to bond the chip to the substrate for high-pin-count devices. Overall, the flip-chip area-array approach allows for more uniform power and ground distribution across the die compared to wire bonding.

So, why hasn’t flip-chip technology become universal since its introduction in the early 1960s? Costs and process complexity have been major hindrances in overcoming wire bond. Every advance in flip-chip technology seems to be matched with an advance in wire bonding.

For instance, the cost of bumping a wafer in flip-chip technology remains the same regardless of the yield. On the other hand, with wire bonding, only good die are subject to the wire bonding cost. Flip-chip processes require tight control of device placement, warpage, fluxing, reflow temperature profiles, flux cleanup, and underfill, adding process complexity. Moreover, each flip-chip die typically requires its own custom substrate, compared to the flexibility of a wire-bonded chip on standard leadframes.

Non-Traditional Flip Chip

Two new technologies, gold-to-gold stud bumping and copper pillar flip chip, enable tighter pitch interconnect (and thus smaller die) than is possible with traditional flip chip, yet still retain its good electrical performance. The bump diameter and process requirements of flip chip normally limit bump pitches to be between 150 to 200 mm.

Differences in the process for copper pillars (plated on the die) followed by a thin cap of solder, versus a standard flip-chip solder bump, enable the tighter pitch (Fig. 1). The tradeoff is a need for tight substrate design pitches and less warpage between the die and substrate to minimize opens with a solder joint that has less collapse height.

1. Copper pillar technology provides very tight pitch interconnection for high-volume products.

Embedded Die Or Embedded Package

In some instances, it can be advantageous to embed a die or package within a PCB-like construction to achieve optimal density. Take Texas Instruments’ MicroSiP (system in package) solution for a dc-dc converter (Fig. 2). A controller package is embedded in a substrate that carries the inductor and capacitors required for switching-supply functions, enabling very high density.

2. Texas Instruments’ TPS82671 MicroSiP contains a power-controller package embedded in an organic substrate with multiple passive components mounted to the surface. It connects to the system PCB via solder balls.

Another type of embedded technology is the eWLB or fan-out wafer-level package (FO-WLP) (Fig. 3). The die are mounted face down on a carrier, over-molded, and separated from the carrier, and interconnections are built on the exposed die surfaces. Both package types gain many signal advantages of flip chip without the process complexity of bumping and flip-chip assembly. Of course, process details must be optimized for successful embedding. However, as mass production brings margins of scale, a robust infrastructure is developing.

3. The FO-WLP is created by mounting multiple die face down on a carrier, overmolding them, removing them from the carrier, and forming a buildup interconnect on the exposed die side.

Multi-Die Interconnects

Multichip die packages containing discrete components, originally called hybrid electronics, have also been around since the 1950s and 1960s. From that time, new technologies have steadily improved the interconnection of multiple die within a single package.

One of the primary goals of multi-die packaging is to reduce PCB area or system volume. Multiple die can be placed side by side on a single leadframe, bonded together, and bonded to the leadframe. Alternatively, die can be stacked vertically—a controller chip is followed by memory on top, all wire bonded to a substrate (Fig. 4).

4. Multiple die can be integrated into a package by stacking and wire bonding them to each other and to the substrate.

Side-by-side and stacked die offer many electrical advantages over standard packages mounted on a PCB. Chief among these are reduced parasitic inductance and capacitance, as well as less time delay between the die that enables faster data rates at lower power consumption. Disadvantages of multichip modules (MCMs) include yield hits and process complexity.

Higher performance levels are being sought with TSV technology (Fig. 5). TSVs provide usable conduction paths vertically through the die and can be area-arrayed.

5. TSV technology offers very high I/O density compared to wire-bonded stacks.

Current pitches of TSVs enable far higher interconnection densities than standard wire-bond or flip-chip technologies. Thus, multiple channels of vertical wide I/O memory buses can feed demanding processors with high-speed data. Thinner die also allow for higher stacking densities, increasing the memory density of a single package.

TSV technologies haven’t permeated the market on a widespread scale as of yet. However, that’s sure to change over the next few years.


A hybrid stacking scheme involves multiple packages stacked on top of each other to achieve the required density (Fig. 6). Using stacked packages, rather than stacked die, makes it possible to source commodity memory chips from any number of suppliers, enabling market forces to drive down costs. The tradeoff is higher complexity at PCB assembly.

6. Package-on-package makes it possible to interconnect products from different vendors, creating mix-and-match flexibility.


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