Switching converters sometimes use soft-start circuitry to reduce the large in-rush current that occurs when they first turn on. By employing a PLD, soft start can be added to power-supply controllers that don't natively support this function, but have an enable or on/off input. This technique creates a pulse-width modulated (PWM) waveform that slowly ramps up from 0% to 100% duty cycle.
The switching supply shown in the figure uses a Linear Technology LT1930ES5 boost converter in a miniature five-pin SOT-23 style package to convert a 3.3-V input to 34 V. The converter operates at 1.2 MHz. When the smallest possible parts are employed, it takes up less than 0.25 in.2 of board space. Although they're not essential for proper circuit operation, L1 and L3 reduce input and output current ripple.
Further design details for the LT1930ES5 may be found in its datasheet. Without the soft-start circuit, the in-rush current spikes to 1.4 A for the first 1 ms before settling to its final value of 0.22 after 2 ms. The soft-start circuit eliminates the spike, and the current slowly ramps up over 8 ms.
The PLD module implements a counter that starts at zero and goes up to its maximum value after the enable input transitions from 0 to 1. A magnitude comparator generates the PWM waveform by comparing the upper- and lower-order N bits. When the upper-order bits are greater than or equal to the lower-order bits, the comparator output is 1, like supply ON.
Four compile-time parameters produce the required hardware. CLOCK_FREQ sets the clock frequency in kilohertz, RAMP_TIME sets the ramp time in milliseconds, and PWM_WIDTH sets the number of steps in the PWM comparison, such as 6 bits yields 26 or 64 steps. PWM_LSB controls the PWM frequency by selecting the low-order bits to be compared. (PWM_LSB = 0 sets the highest possible PWM frequency.)When the PLD compiler generates hardware, it rounds the counter size up to the next power of two. Thus, the ramp produced by the compiled design may take up to twice as long as that specified by the designer. An ASSERT statement in the source code reports the actual implemented ramp time.The PLD code is written in Altera's high-level design language (AHDL) and can be directly compiled into any of Altera's PLDs. (The code is available at www.elecdesign.com.) A design with the parameters specified at the default values takes 31 logic cells in an Altera EP1K50BC256-3—less than 1.5% of the device—and runs at up to 91 MHz. Although the code is written specifically for Altera's devices, the design structure and flow are readily translatable into VHDL or Verilog. Note that some implementations may require a pull-down or pull-up resistor to force the supply OFF while the PLD is being initialized.
The design concept should work in numerous implementations, with different power-supply control ICs or various PLDs. Other sources can generate the PWM waveform too. Among them are a microcomputer using firmware to modulate an output pin, and a microcomputer with an integral timer operating in PWM mode.
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