Need speed? These days, what designer doesn't? It seems that your job primarily revolves around making everything go faster. Of course, faster often equates to increasing difficulty and complexity. The impact of this craze has probably affected the area of data-transmission standards as much as anything else, as both existing and new standards grapple with the thirst for more speed.
THE SERIAL-DATA REVOLUTION
While parallel transmission is theoretically faster, you can only transmit data so far on a wide bus at today's megabit or gigabit data rates. Most designers are happy to get a few inches of bus length in most parallel designs.
The solution? Serial data. Not only are higher speeds possible, but you also can achieve amazingly longer distances.
That's why so much development over the past few years has occurred in older serial-data standards, and why new ones were formed to meet current needs. If you think this isn't a major movement, take a look at the table to see the broad array of options. There's something for everyone, with more on the way.
Designing equipment with high-speed serial interfaces is a new challenge for most engineers, who are more accustomed to designing at lower data rates. When data flies by at more than 1 Gbit/s, it's a whole new world.
Funny enough, if you assume your serial digital data is just a distorted microwave sine wave and resort to RF analysis and measurement techniques, you should be fine. There still are a few issues to account for, though:
- Everything is a transmission line. No longer are interconnects just a piece of wire, a printed-circuit-board (PCB) trace, or a via. At 1 Gbit/s and above, all connections are transmission lines that must be designed and treated as such. Transmission lines have a characteristic impedance that must be matched to the source impedance and load. Also, all lines must be terminated to avoid high standing-wave ratio (SWR) and deadly reflections. On-chip terminations are better than external terminations. Think stripline and microstrip on backplanes. While line lengths of up to several feet have been achieved on backplanes in some designs, attenuation and distortion are horrific. Thanks to skin effect and PCB dielectric losses, attenuation can climb to well over 10 dB/m at rates above 1 Gbit/s.
- There's crosstalk on every line. Crosstalk is a signal that's transferred from a connecting line to one or more adjacent lines through capacitive or inductive coupling. It's best mitigated by keeping lines as far away from one another as possible. As a general rule, make the spacing between adjacent lines at least three times the line width for best results. Ground shields between lines help if they can be used. The two types of crosstalk are near-end crosstalk (NEXT) near the source and far-end crosstalk (FEXT) near an adjacent load.
- Noise is more adverse at these data rates. The wider the bandwidth of any component, circuit, or system, the greater the noise content. Thus, it's essential to start with low-noise components. Using differential transmission lines is also a key noise-reduction method, but good filtering (by passing) and shielding are a must, too. Noise comes from both random and deterministic sources. Random noise is produced by all of the well-known sources, such as thermal noise, semiconductor shot noise, and flicker (1/f) noise. Deterministic noise comes from power-supply feed-through, spurious oscillations, and harmonics and sub-harmonics.
- Connectors are the weak link. We would avoid them if we could, but we can't. They introduce anomalies that produce impedance mismatches and reflections as well as attenuation. Existing connectors barely do the job; thus, special connectors often are the answer.
- Cables are a necessary evil. New and better grades of coax are available. New and updated twisted-pair cable is out there, too. Be sure to choose the best one. Often, another type of special cable is the only solution (e.g., HDMI). Also, remember to keep them short.
- Electromagnetic interference and electromagnetic capability (EMI/EMC) may keep you up at night. EMI is the natural result of using any high-speed serial digital interface. But you will certainly experience EMC issues as you attempt to make your design meet the rules, regulations, and standards certification requirements.
- Clock distribution is more complex. At gigabit speeds, even the shortest connection introduces a delay that can kill a design. The solution lies in equalizing the length of clock lines to the various destinations, but this tends to be difficult if not impossible to accomplish. New clock-distribution ICs can help substantially in this regard. A more recent approach, dynamic phase alignment (DPA), was developed to address the clock-skew problem. Special DPA circuitry inside the transmitter and receiver circuitry monitors the clock and dynamically adjusts its phase in small increments (e.g., 45°) so that it's properly aligned with the data. RapidIO supports DPA, and other standards may eventually follow suit.
- Mind the reduction of supply-line sag and ground bounce. With VCC voltages so low in high-speed serial ICs, it's essential to keep the dc power clean and steady to ensure optimum signal integrity.
- Good PCB design practice is essential to achieve the desired performance level. Good practice includes minimizing vias and connectors, as well as proper termination of all lines. Other essential factors include minimizing parallel-line run lengths, especially on single-ended connections. This keeps clock signals on a single layer, if possible, and puts the VCC on a layer by itself between ground planes. Dedicating full layers to VCC and grounds greatly minimizes noise. FR-4 is still the material of choice, even at these frequencies.
- Spice or other simulation techniques often are used to predict and design high-speed interconnections. But because they use lumped equivalent circuits and unsophisticated transmission line models, these simulations are poor estimators of performance beyond 3 Gbits/s. For higher speeds, electromagnetic field simulation with S-parameters provides more accurate prediction of performance.
- Use corrective measures. Many serial transceivers include built-in pre-emphasis at the transmitter and equalization at the receiver. These circuits can greatly extend the length of the transmission path from a few inches to several feet in some cases while maintaining full signal integrity.
TESTS AND MEASUREMENTS
In most new designs, you'll be designing to meet the specifications of some interface standard. These standards define the characteristics that must be met and, in most cases, what has to be measured to meet them. In all cases, you're trying to optimize the timing budget.
As bit times grow shorter with higher speeds, more of that bit time goes to noise, skew, and jitter and less goes toward the critical setup and hold times required by the bus' various circuits (Fig. 1). Unless these factors are minimized, the desired bit error rate (BER) won't be achieved.
The most important measurements are for jitter and bit error rate. Common measurement procedures include eye diagrams and time-domain reflectometry (TDR).
Jitter refers to the time variations of the leading and trailing edges of the pulses. Its formal definition is "the deviation of the significant instances of a signal from their ideal location in time." "Significant instances" refers to the leading and trailing edges of the data.
Figure 2 shows how jitter and noise affect a high-speed signal. Jitter has always been around, but was largely ignored at lower data rates simply because it was so small compared to the pulse times. With pulses greater than a gigahertz, jitter is a key problem because it eats up so much of the bit time, making clocking ultra-critical.
Jitter often is given as a percentage of the unit interval (UI), where the UI is the bit time. You also will see it expressed as a maximum amount of time (peak-to-peak) variation from a no-jitter version of the signal (picoseconds usually) or as an average (rms) figure derived from statistical measurements.
There are two types of jitter—random and deterministic. Also known as unbounded jitter, random jitter (RJ) is derived from noise of the thermal, shot, and flicker type common in all electronic devices. Also called bounded jitter, deterministic jitter (DJ) comes from crosstalk and either radiated or conducted noise from periodic signals like power-supply ripple, dispersion effects, and impedance mismatches. Then there's data-dependent deterministic jitter that comes from intersymbol interference (ISI), duty-cycle distortion, and pseudorandom bit-sequence periodicity.
Jitter is measured using two basic methods: eye diagrams and jitter analysis software. Both require a very fast real-time digital storage oscilloscope. The eye diagram is formed by capturing and overlaying multiple samples of a long bit stream and then displaying the result (Fig. 3a). The sweep is usually set so that you can see the time interval and both the rising and falling edges of one full bit. Clock triggering should occur at the center of the eye.
Jitter time can be measured at the crossover points. While individual traces are shown here, what you actually see is a wide, fuzzy line tracing the rise, fall, logic-high, and logic-low regions. The wider and "fuzzier" the crossover point, the greater the jitter.
As the data get distorted and bandwidth becomes more limited over distance, the eye begins to close (Fig. 3b). This greatly narrows the area where reliable clocking can occur. Amplitude variations indicate noise (Fig. 3c). A poor signal-to-noise ratio (SNR) can create bit errors. You can compute a noise margin using the expression shown in Figure 3c. Many standards have eye-diagram masks that can help in testing and meeting the specifications.
A key test in today's systems is the stressed eye test, which basically is a receiver test that measures the jitter tolerance. The stress test applies different frequencies and levels of sinusoidal jitter to the test signal and then observes the eye to ensure that clock and data recovery is reliable. Some stress tests also vary the signal's amplitude for further stress analysis.
Another test that can assist in troubleshooting designs is the TDR measurement. A TDR test introduces a fast step function at the input to a transmission line and then uses the scope at the input to monitor potential reflections. These reflections of the step function occur as the result of impedance mismatches, discontinuities in the transmission line (e.g., excessive bends), or the presence of vias.
The TDR will also show reflections because of the mismatches produced by any connectors. Furthermore, because the reflections are based on the length of the time between the launch of the step function and the reflection pulse, you can pinpoint the physical location of the anomaly. With a fast accurate scope, you can zero in on problems within 10 ps and a fraction of a millimeter.
The ultimate test of any high-speed serial system is the bit-error-rate test (BERT), which counts the errors that occur in a given number of bits transmitted. Some standards define a minimum BER in the 10-8 range, but others demand an error ratio of up to 10-12—one in a trillion. Such testing takes hours to complete (do the math), so while it isn't useful in manufacturing testing, it is a must in R&D. The BERT is the final test of the entire system, including ICs, PCBs, connectors, cables, and other structures.
The classical BERT output is the bathtub curve (Fig. 4). This curve is plotted by separating and characterizing the random and deterministic jitter and then computing a time-domain plot that shows the BER for given points along one UI of the signal. With this curve, the eye opening can be determined for a desired BER.
TEST EQUIPMENT ISSUES
To properly view high-speed serial data, the oscilloscope should have a sampling rate that's a minimum of two times the highest data rate and a minimum bandwidth of five times the highest data speed. This will ensure that at least the fifth harmonic can be passed. If you're going to conduct TDR and jitter measurements, you want to be able to view sub-50-ps rise and fall times. A jitter analysis software package is essential.
Next, probes are critical. At high frequencies, interconnections between the equipment being tested and the test instrument must not limit bandwidth or introduce problems. Good probes matched to the scope are a must. Look for differential probes with less than 1 pF of loading capacitance.
A pulse/pattern generator is needed to stimulate the system. The generator must provide the desired range of frequencies and pulse characteristics, like rise/fall times. A pseudorandom bit sequence (PRBS) capability is desirable to create the bit patterns from which the eye diagrams will be formed. A programmable pattern capability is also important. A good pulse generator will either have a feature to vary the jitter or possess an external input to which you can connect a function generator for varying the jitter's frequency (>10 Hz) and amplitude.
A bit-error-rate tester is needed for final overall testing. This device generates a known pattern to stimulate the system and then compares the output to the original input to determine the number of errors. Most testers have built-in scopes and sometimes pulse generators. They also come with standard or supplementary suites of tests, such as jitter analysis, RJ-DJ separation, and eye masks.
Also, use a vector network analyzer (VNA), an instrument typically associated with RF testing and analysis. It's appropriate here because as the high-speed serial digital signals rise in frequency and degrade over the transmission path, they act more like analog microwave RF signals.
A four-port VNA can fully characterize the transmission path. The VNA characterizes the channel in the frequency domain, but conversions to the time domain are possible. The VNA measurements are expressed as S-parameters (S = scattering).
1. Johnson, Howard, Graham, Martin; High-Speed Digital Design, A Handbook of Black Magic; Prentice Hall, 1993
2. Johnson, Howard, Graham, Martin; High-Speed Signal Propagation, Advanced Black Magic; Prentice Hall, 2003