Electronic Design

Semiconductor Packages Shrink Below 1 mm<sup>2</sup>

Move over, SOT23s, SC-70s, and SC-75s. Though your footprints occupy just a few square millimeters of precious board space, you're about to face some tough competition for the title of tiniest discrete-semiconductor package. Recognizing the need for ever smaller package styles, semiconductor manufacturers are paring down case sizes for low-pin-count devices. As a result, designers can expect to soon see diodes and transistors in sub-1-mm2 footprints similar to those of 0402-sized passive components.

A notable recent example is ON Semiconductor's MicroLeadless family of packages. These packages will be fabricated in a new batch-style process that affords several key advantages over existing packaging methods. Their key benefits are low cost, small size, and design flexibility. The degree of miniaturization provided by the MicroLeadless line can be seen in its two- and three-pin versions, which will be offered in 1.0- by 0.5-mm and 1- by 0.6-mm footprints (see the table). These numbers scale up to accommodate devices with higher (but still low) pin counts.

Although the industry has seen some package types that rival the MicroLeadless for small size, the low cost and flexibility of the MicroLeadless process sets it apart from others when it comes to competing with industry-standard plastic packages. The MicroLeadless packages are produced in a wafer-like batch process in which multiple semiconductor die are bonded to a leadframe matrix, wirebonded, and encapsulated (see the figure). Existing wafer tools are used to separate the individual devices. This process saves cost in several ways.

Primarily, it employs a standard-size leadframe to accommodate different-sized die with different lead configurations. This allows common hard tooling across many package configurations and accommodates differences in die size, wiring, and package size through software reprogramming of assembly equipment.

According to Kent Kime, program manager of the packaging platform at ON Semiconductor, a new mold for a traditional package may cost from $100,000 to $150,000 and have a typical lead time of 12 to 16 weeks. Furthermore, installation of a new mold may shut down a production line for the day.

On the other hand, Mi-croLeadless package designs can be implemented very quickly. If the chip can be packaged with an existing leadframe, then production can be set up in perhaps an hour. That's about the time it would take to reprogram the die bonder, wire bonder, and saw to accommodate the new design. Even in a case where a suitable leadframe does not exist, the lead time to generate a new leadframe is still only about two to four weeks.

Another manufacturing advantage is the reduction in materials costs that results from packing chips more densely onto a given size leadframe. Whereas standard leadframe packages may waste 30% to 40% of the raw materials (lead frame and mold compound), the MicroLeadless packages may reduce these losses to just 10%. In terms of device application, MicroLeadless typically im-proves thermal performance by 20% to 30%, Kime says.

While there are other low-I/O packages on the market with similar size and lead types, some of these rely on expensive ceramic substrates with plated through-hole vias for interconnect. BGAs, another possible alternative for shrinking discretes, may also be at a disadvantage as they may require the use of larger than usual, more expensive die to obtain reasonable pitches on the solder balls.

Meanwhile, ON Semiconductor plans to offer its MicroLeadless packages at prices comparable to industry-standard packages. For instance, in the two- and three-pin versions, the new packages will initially be priced about 5% more than SC-75s, with the MicroLeadless packages reaching price parity over time.

However, ON Semiconductor isn't totally alone in its pursuit of tiny, low-cost plastic packaging. This past spring, Infineon Technology announced its thin, small leadless package (TSLP). With its 1.0- by 0.6- by 0.4-mm dimensions, the two- or three-pin TSLP is very similar in size to its MicroLeadless counterpart (see the table, again). Both parts are plastic devices that rely on bond pads rather than extruding leads. Additionally, both MicroLeadless and TSLP compare very favorably in size with established package types like the SC-75.

Both companies are working to introduce their new packages soon. ON Semiconductor is currently sampling its Micro-Leadless products and expects to begin volume production by the end of the year, starting with the smaller packages. For more details, contact Kent Kime at (602) 244-3016 or [email protected]. Meanwhile, Infineon's TSLP is undergoing final qualification, and the company expects to have it in volume production either late this year or early next year. Infineon plans to offer almost all of its small signal silicon components in the TSLP. For additional information, see www.infineon.com/products/discrete/TSLP/.

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