SERDES Chip Upgrades Backplanes To 6 Gbits/s

Networking equipment manufacturers who want to enhance their current backplanes to support higher data rates—yet still remain backward-compatible with installed line cards—can look to the PM8359 Quad PHY 6G. Developed by PMC-Sierra, it multiplexes and demultiplexes eight 3.125-Gbit/s serial links into four 6.25-Gbit/s serial links (see the figure).

Due to its flexible design, the chip can fit into just about any product, including Ethernet switches; storage systems using Fibre Channel, ISCSI, SATA, and SAS; servers using new serial bus standards like InfiniBand, PCI-Express, or RapidIO; and Sonet/SDH add/drop multiplexers. The PM8359 also is the first device to comply with the Optical Internetworking Forum (OIF) Common Electrical I/O (CEI) + Long Reach specification. CEI 6+ defines a method of driving gigabit serial signals across a backplane at distances up to one meter. The 6.25-Gbit/s data rate is defined for standard NRZ binary signaling rather than some multilevel pulse-amplitude modulation scheme used by other 6-Gbit/s serializer/deserializer (SERDES) chips.

Adaptive decision feedback equalization (DFE) helps generate the 6.25-Gbit/s speed with a bit-error rate of 10⁻¹⁸. The QuadPHY 6G DFE is a nonlinear equalization technique that overcomes intersymbol interference (ISI), which shuts the eye of an eye diagram at the receiver. The DFE circuits (not shown in the figure) estimate the DFE coefficients from the received symbol sequence with adaptive algorithms and then adjust the signal to keep the eye open. The advantage of nonlinear DFE is that it enhances only the signal, not the noise.

The PM8359 is made with 0.13-µm CMOS. It comes in a 19- by 19-mm 320-pin flip-chip ball grid array (FCBGA). Engineering samples are available now for $250. An evaluation board using the new 6+ Molex connectors costs $4900.