Electronic Design

SERDES IP Releases Tackle Top Speeds

High-speed design and serial buses used for chip-to-chip communications seem to go hand in hand nowadays. Whether youâ??re talking signal integrity, printed-circuit board (PCB) routability, or a slew of other factors, it just makes sense. Therefore, the ready availability of reliable serializaer/deserializer (SERDES) intellectual property (IP) is imperative.

Tundra Semiconductorâ??s Silicon Logic Engineering (SLE) division addresses this need with an Interlaken IP core capable of 150 Gbits/s (see the figure). Originally developed by Cortina Systems, the Interlaken protocol is a royalty-free specification that combines the SPI-4.2 and XAUI architectures, which have seen high adoption rates in networking systems.

SLEâ??s core is fully scalable, making it a good fit for future network equipment designs, such as switches, routers, and storage devices. Each one of its 24 lanes is capable of 3.125 to 6.375 Gbits/s. When all 24 lanes are chugging at full speed, the raw data rate equals just over 150 Gbits/s, which is the fastest rate possible according to SLE.

Other features include support for up to 64k channels, a continuous meta frame for programming frequency allowing for lane alignment, and 64B/67B data encoding and scrambling. SLEâ??s Interlaken IP core should pop into just about any ASIC, and it works with off-the-shelf SERDESs from most vendors. Itâ??s available through SLEâ??s sales channel.

If network storage is your game, then you realize that data bandwidth and processing expectations have skyrocketed over the past few years, with power consumption and form factor expected to remain constant. Again, the trend is to include a high-speed SERDES to help meet these requirements.

Recently, eSilicon partnered with Avago to license its embedded SERDES cores targeted at the network storage, communications, and high-performance computing markets. The multitude of SERDES offerings includes 90- and 65-nm CMOS processes available from TSMC.

This sixth-generation suite of offerings has been road tested in many products. Avago offers its cores at rates from 1.0625 to 10.51875 Gbits/s, and the company claims they provide strong signal integrity and jitter performance. Other features include an adaptive feedback equalizer in the receiver, programmable transmitter pre-emphasis, and a bit error rate of less than 10-17. A broad selection of Avago SERDES cores over a range of data rates and protocol standards is available from eSilicon (see the table).

SILICON LOGIC ENGINEERING

siliconlogic.com/asic_fpga_interlaken_core.asp

ESILICON

esilicon.com/offerings/avago.php

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