Today, high-speed field-programmable-gate-array (FPGA) designers encounter signal-integrity (SI) issues with increasing frequency. Unfortunately, the first indication of such a problem is often a prototype that works intermittently or has an unacceptably slow clock speed. In production, yields may be low or parts could have early mortality in the field.
Why do so many high-speed FPGA designs suffer from SI problems? The answer is simply that signal edge rates are faster than ever before. The quicker the edge rate, the more likely that SI failures will occur.
Designers certainly want to prevent these failures. Ninety percent of the solution lies in identifying potential problems before the first prototype is even constructed. This is particularly true for SI problems because intermittent failures are difficult to troubleshoot on a prototype. Fortunate is the designer who performs virtual prototyping, which entails simulating SI on critical nets and boards. Because problems can be fixed during design, the number of prototype turns due to SI issues can be reduced significantly. One company went from 94% prototyping failures to less than 1% by merely implementing virtual prototyping.
Early detection of SI problems can result in large cuts in cost. Reducing the prototype turns leads to tremendous savings on board stuffing, redesign, layout revisions, and retesting. And when designs are completed more quickly, obviously products can reach the market sooner, enabling the company to reach critical market windows.
Beware of SI Effects
The effects of SI are often categorized as overshoot, undershoot, and ringing on nets with fast drivers (Fig. 1). Crosstalk may appear as an overshoot or an undershoot, or it may just affect timing to the point that the logic no longer operates correctly.
Overshoot doesn't cause logic failures in most designs. Large overshoots can clear latches, though, and lead to apparent data faults. If overshoot causes clamp diodes to turn on, receivers can slow down. This results in timing problems at desired system clock speeds. Repeated large overshoots damage clamp diodes, which can end with early mortality in the field.
Ringing can make a signal go into the "no-man's land" between VIL and VIH. Because the logic threshold for an input is between these voltages, this signal is subject to misinterpretation. Consequently, a clock may appear to change state, loading data into a latch. A data line may be misinterpreted, resulting in the capture of an invalid value.
Crosstalk can lead to overshoot or undershoot on a quiescent, or non-switching, net. This is distinguishable from problems begun by SI because crosstalk results from the switching of neighboring nets, rather than the net itself. Plus, crosstalk can bring about setup-and-hold timing failures. Interactions between a switching net and its switching neighbors can lead to variations in delay of 5:1 or more (Fig. 2).
Effects Of SI And Crosstalk
SI and crosstalk effects are more pronounced on longer nets. There's a critical length below which SI effects are generally tolerable. This critical length is equivalent to (1/6) × (V/TR), where TR is the signal rise time and V is the speed of the signal in the transmission line. That's 0.5 to 0.8 times the speed of light in free space. For a 1-ns edge and FR-4 (εR = 4.7), the critical length is (1/6) × \[(5.5 in./ns)/1 ns\], or 0.9 in. For routed nets longer than the critical length, it's usually necessary to terminate the net to reduce SI and crosstalk effects.
Many logic families have fast enough edge rates to cause SI problems. The I/O logic levels and edge rates are determined by the modules that are connected on the board, so the designer has a limited number of choices. Interface specifications operating above 50 MHz (the fastest edge rates below 2 ns) are at a higher risk. Designers who watch for fast edge rates and clock speeds and address SI early in the design have better chances at creating working prototypes.
SI and crosstalk problems are caused by dV/dt and dI/dt effects. Logic families with higher-voltage swings, such as 5-V CMOS, will experience problems at lower frequencies of 20 to 30 MHz. But critical lengths will be relatively long. Logic families with lower-voltage swings, like LVDS, will have problems only at higher edge rates, but critical lengths will be shorter. Even a 1-MHz signal can have SI problems if the driver has an edge rate of 3 V/ns.
Once the I/O specification is selected, the designer can decide to make tradeoffs between the driver characteristics and the needed additional components on the board. The driver strength and speed can be traded as well. Furthermore, they can be swapped for required termination components to achieve the desired SI. For instance, a slow, low-drive strength driver may not produce SI problems. Yet, it may be too slow in the circuit. The designer might then choose a faster edge rate or a higher drive strength. Generally, the faster driver edge rate is more likely to necessitate the adding termination components onto your board and, hence, its valuable space will be used up.
SI problems can be reduced by selecting a lower-swing logic family and the slowest-driver edge rate that's compatible with design requirements. In many applications, a slower driver with a higher drive strength is preferable to a faster driver with a lower drive strength. This has the added benefit of lowering the number of nets longer than the critical length. Long nets are most likely to require termination, so selecting a slower driver will, in turn, help reduce board area.
Problematic nets are those with the fastest edge rates. These nets require careful simulation to ensure proper termination. The critical nets usually include clock and clock enable lines, because these are driven by high-current drivers and have long lengths due to fanout requirements. With long net lengths, address and data buses cause concern as well. As a result of the designer's driver selection, the edge rates of the data lines may be the same as the clock, even though the clock might switch more. This is an ideal example of an appropriate situation to have slower drivers for non-clock nets.
Prior to layout, problematic nets can be identified and layout rules generated. For instance, an address bus length could be shortened significantly by repositioning a component on the board or by swapping pins on the FPGA. After the nets with high-speed drivers have been identified, those likely to exceed the critical length can be assigned a termination style, like a series resistor at the driver or an RC load at the receiver. By simulating and optimizing terminations early in the design, the layout designer will be able to include those nets.
Simulation of SI demands suitable simulation models. Drivers and receivers most commonly use the I/O Buffer Information Specification (IBIS), also known as the EIA 656. The IBIS models describe the characteristics at the I/O pin using V/I and V/T tables. Unlike Spice, these models don't include topology information. Semiconductor vendors, therefore, are more willing to provide their customers with these.
Once the critical nets are identified and the IBIS models are obtained, simulation is ready to begin. By simulating the net in LineSim using the slowest acceptable edge rate and lowest-drive-strength drivers, you can determine the optimum routing and termination strategies. A clock net, for example, might be star-routed rather than daisy-chain-routed to reduce clock skew. Then, the star route can be terminated at each receiver to minimize the impact of unequal-length legs in the layout.
To obtain the best possible agreement between simulation and lab testing, it's important to include scope-probe loading in the simulation. Typically, a 3-pF scope model can be used.
The Impact Of Edge Rates
Next, the effect of changing the edge rate can be determined. Edge rates may vary 5:1 or more for a driver part, depending on the IC process corner, temperature, and power-supply voltage. This can largely impact pin-to-pin delay and rise/fall times at the receivers. After that, the drive strength can be increased until the signal time of flight and rise/fall time meets the system demands. The ability to increase/decrease the drive strength requires an FPGA with Xilinx Virtex-like output characteristics.
To establish the actual delays, system timing must be corrected from the data book delays, which assume a purely capacitive load. The actual delays include the travel delay down the transmission line, as well as the loading of the receiver. To do this, subtract the portion of the delay due to the capacitive load, and then add the delay due to the actual load. These delays can be obtained by using an SI simulator and drivers selected to meet timing requirements. This is discussed in further detail in the HyperLynx Technical Application Note, "Flight Time Correction."
At this point, the SI can be checked to make sure overshoot and undershoot limits haven't been exceeded. Crosstalk effects can be simulated through estimated routing spacing. Layout rules for lengths and spacing for critical nets can be passed to the layout group. In addition, requirements for board stackup, such as layer assignment of certain critical nets, dielectric thickness, and impedance tol-erances, can be documented for production.
When the layout is complete, simulation can be performed on real routed nets with BoardSim. The layout file is translated into an HYP file for simulation. Again, SI is checked and termination components are added or modified as necessary. Driver selections can be updated to meet system timing requirements in the actual layout. Crosstalk effects on noise for quiescent nets and timing for switching nets can be evaluated as well, because actual wire widths and spacings are known. Final timing checks are able to be made using results from simulation, including updated termination components, chosen drivers, and flight time corrections.
If SI or crosstalk issues still exist, selected nets can be simulated in LineSim. There, net spacing can be varied to improve crosstalk, or new termination strategies might be tried quickly to improve SI and timing. Sometimes, it's necessary to move a net to the other side of a ground plane to eliminate crosstalk with a neighbor. Other times, rerouting a net or modifying a termination strategy helps the board to pass SI and timing requirements.
There are many ways to reduce SI and crosstalk problems. Aside from placing a ground (VCC) plane between two nets to eliminate coupling, the spacing of high-speed nets may also be increased. For EMI, all fast nets can be placed inside a sandwich of planes.
In high-speed nets with a fanout of two, it's possible to lessen reflections at the bifurcation point. That's accomplished by increasing the impedance of the fanout traces to 2 × (Z0). The two fanout routes appear in parallel, which effectively terminates the driver transmission line with Z0 at the bifurcation point. Both of the fanout traces should then be terminated in their characteristic impedance of 2 × (Z0).
Note that to change line impedance, the trace width from the driver to the split must be much wider than the trace width from the split to the receivers. As an alternative, the bifurcation point can be kept shorter than the critical length (1/6) × (V/TR) from the driver.
Bidirectional buses should be terminated at both ends for optimal SI. For a board that drives banks of DRAM modules in very tight space, it's possible to terminate the bus at just the address-driver end, if the net isn't too long.
Terminations can include any passive component. The advantage comes in mixed-signal circuits when LineSim can be used to model the interface to an analog component. For example, the input impedance, such as the R/2R input stage of a digital-to-analog converter (DAC), can be modeled in LineSim. Comparisons between simulation and test data will be valid if the analysis includes the test probes, as well as the transmission lines, drivers, and receivers. SI analysis addresses both timing and overshoot/undershoot (Fig. 3).
Using simulation for virtual prototyping helps identify and prevent SI problems up front, before the first prototype is built. By following the tips presented here, you can address design issues before they become problems. This will ensure that your high-speed designs are done right the first time. So, you can spend less time redesigning and more time working on your next project.