A photodiode combined with two op amps and a comparator helps form a fiber-optic receiver capable of data rates to 800 kbits/s (Fig. 1). Small packages (SOT23-5 for the op amps; µMAX-8 for the comparator) minimize the required real estate on a pc board or hybrid substrate.
The photodiode operates in the photo-conductive mode, producing a signal voltage at IC1 with a transimpedance gain that’s equal to the value of R1 (4.7 kΩ in this case). The op amps (IC1 and IC2) are configured as noninverting amplifiers with gains of approximately 25 V/V each, so the circuit’s overall transimpedance gain is just under 3 MΩ: 4700 Ω × 25 × 25 = 2.99 MΩ. The op amps’ gain-bandwidth capability sets the maximum practical data rate at 800 kbits/s.
Capacitive coupling between IC1 an IC2 negates the amplification of IC1’s offset voltage. To achieve an optimum signal amplitude and symmetry, the R6/R11 divider sets IC2’s reference voltage at 2.5 V. The R12/R13 divider, which sets the comparator's reference somewhat higher (2.6 V), provides a noise margin for the system and ensures that the comparator output remains low during a “no signal” condition.
Capacitive coupling can’t maintain a dc signal; instead, it allows dc portions of the signal to “relax” toward the reference level (Fig. 2). This effect, particularly noticeable for signals that appear after a long quiet period, is directly affected by the R7/C3 time constant. R7/C3 should be as large as possible to minimize the relaxation effect, but R7 should remain approximately 10 kΩ(to minimize offset voltage by matching the inverting-input source resistance). The comparator can’t switch when its input is below the reference level, so too much relaxation can cause a loss of data at the end of a long string of 1’s or 0’s (Fig. 3).
Again, the IC3 reference should be slightly higher than the IC2 reference for a logic-low no-signal output (otherwise, set the IC3 reference lower). This ΔVREF provides a system noise margin that you can adjust via the R12/R13 divider, but be aware of the trade-off. Setting ΔVREF too low allows erroneous output transitions, and setting the value too high degrades timing of the received signal. Set ΔVREF as low as possible without causing erroneous transitions, making allowance for the offset voltage in IC2 and IC3.
The system is designed for 5-V operation, but with a minor degradation in data rate, it can operate at 3.3 V or even 3 V. Lowering the supply voltage increases the photodiode’s internal capacitance (inversely proportional to the applied bias voltage), which forms a low-pass pole with R2 that limits the photodiode’s frequency response. To a lesser degree, the lower supply voltage also limits response by producing a smaller gain-bandwidth product in the amplifiers. The circuitry is designed to accommodate a change in supply voltage with only one adjustment: ΔVREF changes with supply voltage, so you must adjust the R12/R13 divider as required to reestablish the desired noise margin.