Electronic Design

SoC/ASIC Prototyping System Targets Designs Up To 9 Mgates

Designed to debug and verify system-on-a-chip (SoC) designs of diverse styles up to 9 million ASIC gates in size, GiDEL’s PROC9M prototyping system operates at system clock speeds up to 300 MHz.

Each system includes an enclosed card cage for one to three of GiDEL’s recon- figurable PROC3M FPGA boards, rated at 3 million ASIC gates. Each board has a pair of interconnected, high-speed Altera Stratix II EP2S180 FPGAs and 256 Mbytes of onboard DRAM or 768 Mbytes for each full PROC9M module.

The PROC9M includes a full suite of tools for implementing and debugging designs as well as the PROCM Developer’s Kit, which provides various methods of capturing data and debugging designs. The kit consists of a suite of tools for the efficient mapping of chip designs into PROC9M FPGAs and for debug.

The system architecture eliminates the delays inherent in routing chips and programmable backplanes found in legacy emulation systems and fixed-interconnect prototyping boards. Users connect the FPGAs in a pattern that matches the topology of their design, rather than trying to fit the design to a fixed system topology (see the figure).

The PROC3M boards have 261 I/O pins connecting the FPGAs to each other. Each FPGA also has six 118-pin connectors for users to make their FPGA interconnections or to connect the system to a target system environment.

The configured system looks like a sea of programmable devices interconnected through one or more “user-designated buses” of 118 pins. With up to 4248 user-accessible I/Os per full PROC9M system, there are plenty of I/Os to interface to target systems for fast in-circuit verification.

Delivery times are four to six weeks from receipt of order. Prices start at about $25,000.

GiDEL Ltd.
www.gidel.com

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